Техническая Спецификация для Linear Technology LTC4278 IEEE802.3at PD Controller with 12V Aux, Vout = 5V, Iout = 4.5A DC1561B DC1561B

Модели

DC1561B

LTC4278

4278fc

PIN FUNCTIONS

SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary

power application. Drive SHDN high to disable LTC4278

operation and corrupt the signature resistance. If unused,

tie SHDN to V

PORTN

T2P (Pin 2): Type 2 PSE Indicator, Open-Drain. Low imped-

ance indicates the presence of a Type 2 PSE.
R

CLASS

(Pin 3): Class Select Input. Connect a resistor

between R

CLASS

and V

PORTN

to set the classification load

current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
V

PORTN

(Pins 5, 6): Input Voltage, Negative Rail. Pin 5

and Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin

provides an output signal for a secondary-side synchro-

nous rectifier. Large dynamic currents may flow during

voltage transitions. See the Applications Information

section for details.
V

(Pin 10): Supply Voltage Pin. Bypass this pin to

GND with a low ESR ceramic capacitor. See the Applica-

tions Information section for details.
t

(Pin 11): Pin for external programming resistor to

set the minimum time that the primary switch is on for

each cycle. Minimum turn-on facilitates the isolated feed-

back method. See the Applications Information section

for details.
ENDLY (Pin 12): Pin for external programming resistor to

set enable delay time. The enable delay time disables the

feedback amplifier for a fixed time after the turn-off of the

primary-side MOSFET. This allows the leakage inductance

voltage spike to be ignored for flyback voltage sensing.

See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to

synchronize the internal oscillator with an external clock.

The positive edge of the clock causes the oscillator to dis-

charge causing PG to go low (off) and SG high (on). The

sync threshold is typically 1.5V. Tie to ground if unused.

See the Applications Information section for details.

SFST (Pin 14): Soft-Start. This pin, in conjunction with a

capacitor (C

SFST

) to GND, controls the ramp-up of peak

primary current through the sense resistor. It is also used

to control converter inrush at start-up. The SFST clamps

the V

CMP

voltage and thus limits peak current until soft-

start is complete. The ramp time is approximately 70ms

per µF of capacitance. Leave SFST open if not using the

soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an

external capacitor (C

OSC

) to GND, defines the controller

oscillator frequency. The frequency is approximately

100kHz • 100/C

OSC

(pF).

FB (Pin 16): Feedback Amplifier Input. Feedback is usually

sensed via a third winding and enabled during the flyback

period. This pin also sinks additional current to compensate

for load current variation as set by the R

CMP

pin. Keep the

Thevenin equivalent resistance of the feedback divider at

roughly 3k.
V

CMP

(Pin 17): Frequency Compensation Control. V

CMP

is used for frequency compensation of the switcher con-

trol loop. It is the output of the feedback amplifier and

the input to the current comparator. Switcher frequency

compensation components are placed on this pin to GND.

The voltage on this pin is proportional to the peak primary

switch current. The feedback amplifier output is enabled

during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider

from V

PORTP

to this pin sets an undervoltage lockout based

upon V

PORTP

level (not V

). When the UVLO pin is below

its threshold, the gate drives are disabled, but the part

draws its normal quiescent current from V

The bias current on this pin has hysteresis such that the

bias current is sourced when UVLO threshold is exceeded.

This introduces a hysteresis at the pin equivalent to the bias

current change times the impedance of the upper divider

resistor. The user can control the amount of hysteresis

by adjusting the impedance of the divider. Tie the UVLO

pin to V

if not using this function. See the Applications