Техническая Спецификация для Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI
Модели
MEGA328P-XMINI
27
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
9.
System Clock and Clock Options
9.1
Clock Systems and their Distribution
presents the principal clock systems in the AVR and their distribution. All of the clocks need not be
active at a given time. In order to reduce power consumption, the clocks to modules not being used can be
halted by using different sleep modes, as described in
halted by using different sleep modes, as described in
. The
clock systems are detailed below.
Figure 9-1.
Clock Distribution
9.1.1
CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
modules are the General Purpose Register File, the Status Register and the data memory holding the Stack
Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.
9.1.2
I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is
also used by the External Interrupt module, but note that start condition detection in the USI module is carried
out asynchronously when clk
also used by the External Interrupt module, but note that start condition detection in the USI module is carried
out asynchronously when clk
I/O
is halted, TWI address recognition in all sleep modes.
Note:
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in
enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of
the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the
SUT and CKSEL Fuses as described in
.
General I/O
Modules
Asynchronous
Timer/Counter
Timer/Counter
CPU Core
RAM
clk
I/O
clk
ASY
AVR Clock
Control Unit
clk
CPU
Flash and
EEPROM
EEPROM
clk
FLASH
Source clock
Watchdog Timer
Watchdog
Oscillator
Reset Logic
Clock
Multiplexer
Watchdog clock
Calibrated RC
Oscillator
Timer/Counter
Oscillator
Crystal
Oscillator
Low-frequency
Crystal Oscillator
External Clock
ADC
clk
ADC
System Clock
Prescaler