Техническая Спецификация для Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
10.11.2 MCUCR – MCU Control Register
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see 
Writing to the BODS bit is controlled by a timed sequence and an enable bit, BODSE in MCUCR. To disable 
BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, 
BODS must be set to one and BODSE must be set to zero within four clock cycles. 
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is 
active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three 
clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by 
a timed sequence.
Note:
1. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P
10.11.3 PRR – Power Reduction Register
• Bit 7 – PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI 
again, the TWI should be re initialized to ensure proper operation.
• Bit 6 – PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2 is 0). When the 
Timer/Counter2 is enabled, operation will continue like before the shutdown.
• Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, 
operation will continue like before the shutdown.
• Bit 4 – Reserved 
This bit is reserved in ATmega48A/PA/88A/PA/168A/PA/328/P and will always read as zero.
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, 
operation will continue like before the shutdown. 
Bit
7
6
5
4
3
2
1
0
BODS
BODSE
PUD
IVSEL
IVCE
MCUCR
Read/Write
R
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
PRTWI
PRTIM2
PRTIM0
PRTIM1
PRSPI
PRUSART0
PRADC
PRR
Read/Write
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0