Техническая Спецификация для Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI

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ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

The ports are bi-directional I/O ports with optional internal pull-ups. 

 shows a functional description of 

one I/O-port pin, here generically called Pxn.

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

I/O

, SLEEP, and PUD are 

common to all ports.

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in 

, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and 

the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is 
configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin. 

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To 
switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output 
pin. The port pins are tri-stated when reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If 
PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). 

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the 
SBI instruction can be used to toggle one single bit in a port.

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx:

WRITE DDRx

WRx:

WRITE PORTx

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

PUD:

PULLUP DISABLE

clk

I/O

:

I/O CLOCK

RDx:

READ DDRx

D

L

Q

Q

RESET

RESET

Q

Q

D

Q

Q

D

CLR

Q

Q

D

CLR

D

ATA

 B

U

S

SLEEP

SLEEP:

SLEEP CONTROL

Pxn

WPx

0

1

WRx

WPx:

WRITE PINx REGISTER