Техническая Спецификация для Intel 1.40 GHz RH80532NC017256
Модели
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ) in
Micro-FCBGA and Micro-FCPGA Packages Datasheet
14 Datasheet
298517-006
2.1.5
Signal Differences Between the Mobile Intel Celeron Processor
(0.18 µ) (in BGA2 and Micro-PGA2 Packages) and the Mobile
Intel Celeron Processor (0.13 µ) (in Micro-FCBGA and Micro-
FCPGA Packages)
(0.18 µ) (in BGA2 and Micro-PGA2 Packages) and the Mobile
Intel Celeron Processor (0.13 µ) (in Micro-FCBGA and Micro-
FCPGA Packages)
A list of new and changed signals is shown in Table 1.
Table 1. New and Revised Mobile Intel Celeron Processor (0.13 µ) Signals
Signals Function
BCLK, BCLK# Differential host clk signals.
CLKREF
Host Clock reference signal in Single Ended Clocking mode.
BSEL[1:0]
Signals are output only instead of I/O. Please refer to the Appendix for details.
DPSLP#
Deep Sleep pin (replaces SLP# pin on the mobile Celeron processor (0.18 µ))
NCTRL
AGTL output buffer pull down impedance control.
VID[4:0]
Voltage Identification (different implementation from mobile Celeron processor (0.18 µ)). Please refer
to Section 3.2.3 for details.
to Section 3.2.3 for details.
VTTPWRGD
Power Good signal for VCCT, which indicates that, the VID signals are stable. Please refer to Figure
3 for VTTPWRGD system level connections.
3 for VTTPWRGD system level connections.
2.2 Power
Management
2.2.1
Clock Control Architecture
The Mobile Intel Celeron Processor clock control architecture (Figure 1) has been optimized for leading
edge mobile computer designs. The clock control architecture consists of six different clock states:
Normal, Auto Halt, Quick Start, HALT/Grant Snoop and Deep Sleep states. The Auto Halt state
provides a low-power clock state that can be controlled through the software execution of the HLT
instruction. The Quick Start state provides a very low power and low exit latency clock state that can be
used for hardware controlled “idle” computer states. The Deep Sleep state provides extremely low-
power states that can be used for “Power-On-Suspend” computer states, which is an alternative to
shutting off the processor’s power. The exit latency of the Deep Sleep state is 30 msec in the Mobile
Intel Celeron Processor. Performing state transitions not shown in Figure 1 is neither recommended nor
supported. Figure 2 provides the clock state characteristics, which are described in detail in the following
sections.
edge mobile computer designs. The clock control architecture consists of six different clock states:
Normal, Auto Halt, Quick Start, HALT/Grant Snoop and Deep Sleep states. The Auto Halt state
provides a low-power clock state that can be controlled through the software execution of the HLT
instruction. The Quick Start state provides a very low power and low exit latency clock state that can be
used for hardware controlled “idle” computer states. The Deep Sleep state provides extremely low-
power states that can be used for “Power-On-Suspend” computer states, which is an alternative to
shutting off the processor’s power. The exit latency of the Deep Sleep state is 30 msec in the Mobile
Intel Celeron Processor. Performing state transitions not shown in Figure 1 is neither recommended nor
supported. Figure 2 provides the clock state characteristics, which are described in detail in the following
sections.
2.2.2 Normal
State
The Normal state of the processor is the normal operating mode where the processor’s core clock is
running and the processor is actively executing instructions.
running and the processor is actively executing instructions.
2.2.3 Auto
Halt
State
This is a low-power mode entered by the processor through the execution of the HLT instruction. A
transition to the Normal state is made by a halt break event (one of the following signals going active:
NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).
transition to the Normal state is made by a halt break event (one of the following signals going active:
NMI, INTR, BINIT#, INIT#, RESET#, FLUSH#, or SMI#).