Техническая Спецификация для Intel 850 MHz KC80526NY850128
Модели
KC80526NY850128
R
14
Mobile Intel® Celeron® Processor Specification Update
S = 64-bit Intel
®
Xeon™ processor with 800 MHz system bus
T = Mobile Intel
®
Pentium
®
4 processor – M
U = Unannounced 64-bit Intel
®
Xeon™ processor MP
V = Mobile Intel
®
Celeron
®
processor on 0.13 micron process in micro-FCPGA package
W = Intel
®
Celeron
®
M processor
X = Intel
®
Pentium
®
M processor on 90 nm process with 2-MB L2 cache
Y = Intel
®
Pentium
®
M processor
Z = Mobile Intel
®
Pentium
®
4 processor with 533 MHz system bus
AA = Intel
®
Pentium
®
processor Extreme Edition and Intel
®
Pentium
®
D processor on 65 nm
process
AB = Intel
AB = Intel
®
Pentium
®
4 processor on 65 nm process
AC = Intel
®
Celeron
®
Processor in 478 Pin Package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel
AE = Intel
®
Core™ Duo processor and Intel
®
Core™ Solo processor on 65 nm process
AF = Dual-Core Intel
®
Xeon
®
processor LV
AG = Dual-Core Intel® Xeon® Processor 5100 Series
AH = Intel® Core™2 Duo mobile processor
AI = Intel® Core™2 Extreme Processor X6800
Δ
and Intel® Core™2 Duo Desktop Processor
E6000
Δ
Sequence
AL = Dual-Core Intel® Xeon® Processor 7100 Series
Z = Mobile Intel® Pentium® 4 Processor with 533 MHz System Bus. The Specification Updates for the
Pentium
Pentium
®
processor, Pentium
®
Pro processor, and other Intel products do not use this convention.
NO.
BA2
PA2
MA2
BB0
PB0
MB0
BC0
PC0
MC0
BD0
PD0
FBD
O
FPDO
FBA1
FPA1
FBB1
FPB1
Plans
ERRATA
M1
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
FP data operand pointer may be
incorrectly calculated after FP
access which wraps 64-Kbyte
boundary in 16-bit code
incorrectly calculated after FP
access which wraps 64-Kbyte
boundary in 16-bit code
M2
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Differences exist in debug exception
reporting
reporting
M3
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Code fetch matching disabled debug
register may cause debug exception
register may cause debug exception
M4
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Double ECC error on read may
result in BINIT#
result in BINIT#
M5
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
FP inexact-result exception flag may
not be set
not be set
M6
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
BTM for SMI will contain incorrect
FROM EIP
FROM EIP
M7
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
I/O restart in SMM may fail after
simultaneous MCE
simultaneous MCE
M8
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Branch traps do not function if BTMs
are also enabled
are also enabled
M9
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
Machine check exception handler
may not always execute successfully
may not always execute successfully
M10
X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NoFix
MCE due to L2 parity error gives L1
MCACOD.LL
MCACOD.LL