Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet 1 of 2

May 2012

14

Document Number: 327405

-

001

PCU

Power Control Unit

Rank

A unit of DRAM corresponding four to eight devices in parallel, ignoring 

ECC. These devices are usually, but not always, mounted on a single side of 

a DIMM.

SCI

System Control Interrupt. Used in ACPI protocol.

Storage Conditions

A non-operational state. The processor may be installed in a platform, in a 

tray, or loose. Processors may be sealed in packaging or exposed to free air. 

Under these conditions, processor landings should not be connected to any 

supply voltages, have any I/Os biased or receive any clocks. Upon exposure 

to “free air” (i.e., unsealed packaging or a device removed from packaging 

material) the processor must be handled in accordance with moisture 

sensitivity labeling (MSL) as indicated on the packaging material.

SVID

Serial Voltage Identification 

System Agent

Consists of all the uncore functions within the processor other than the 

cores and cache. This includes the integrated memory controller, PCIe 

controller, PCU, etc.

TDP

Thermal Design Power.

TDC

Thermal Design Current is the maximum current that the VR must be 

thermally capable of sustaining indefinitely in the worst-case thermal 

environment defined for the platform.

TPM

Trusted Platform Module

V

CC

Processor core power supply.

V

SS

Processor ground.

V

TT

L3 shared cache, memory controller, and processor I/O power rail.

V

DDQ

DDR3 power rail.

V

CCSA

System Agent (memory controller, DMI and PCIe controllers) power supply

V

CCIO

High Frequency I/O logic power supply

V

CCPLL

PLL power supply

x1

Refers to a Link or Port with one Physical Lane.

x4

Refers to a Link or Port with four Physical Lanes.

x8

Refers to a Link or Port with eight Physical Lanes.

x16

Refers to a Link or Port with sixteen Physical Lanes.