Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

154

Document Number: 327405

-

001

B/D/F/Type:

0/0/0/PCI

Address Offset:

CC-CDh

Default Value:

0000h

Access:

RO; RW

Size:

16 bits

BIOS Optimal Default

0000h

This register enables various errors to generate an SMI DMI special cycle. When an 

error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI 

special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers respectively. 

One and only one message type can be enabled.

15:2

RO

0h

Reserved (RSVD) 

1

RW

0b

Uncore

SERR Multiple-Bit DRAM ECC Error (DMERR):

1 = The Host Bridge generates an SERR message 

over DMI when it detects a multiple-bit error 

reported by the DRAM controller.

0 = Reporting of this condition via SERR messaging is 

disabled.

For systems not supporting ECC, this bit must be 

disabled.

0

RW

0b

Uncore

SERR on Single-bit ECC Error (DSERR):

1 = The Host Bridge generates an SERR special cycle 

over DMI when the DRAM controller detects a 

single bit error.

0 = Reporting of this condition via SERR messaging is 

disabled.

For systems that do not support ECC, this bit must be 

disabled.

15:2

RO

0h

Reserved (RSVD) 

1

RW

0b

Uncore

SMI on Multiple-Bit DRAM ECC Error (DMESMI):

1 = The Host generates an SMI DMI message when it 

detects a multiple-bit error reported by the DRAM 

controller.

0 = Reporting of this condition via SMI messaging is 

disabled. For systems not supporting ECC, this bit 

must be disabled.

0

RW

0b

Uncore

SMI on Single-bit ECC Error (DSESMI):

1 = The Host generates an SMI DMI special cycle 

when the DRAM controller detects a single bit 

error.

0 = Reporting of this condition via SMI messaging is 

disabled. For systems that do not support ECC, 

this bit must be disabled.