Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

157

B/D/F/Type:

0/0/0/MCHBAR MC1

Address Offset:

44C8-44CBh

Default Value:

00000000h

Access:

ROS-V

Size:

32 bits

BIOS Optimal Default

0000h

This Channel 1 register is used to store the error status information in ECC enabled 

configurations, along with the error syndrome and the rank and bank address 

information of the address block of main memory of which an error (single bit or multi-

bit error) has occurred. The address fields represent the address of the first single or 

the first multiple bit error occurrence after the error flag bits in the ERRSTS register 

have been cleared by software. A multiple bit error will overwrite a single bit error. 

Once the error flag bits are set as a result of an error, this bit field is locked and doesn't 

change as a result of a new error until the error flag is cleared by software. Same is the 

case with error syndrome field.

31:16

ROS-V

0000h

Powergood

Error Column (ERRCOL):
This field holds the DRAM column address of the 

read transaction that had the ECC error.

15:0

ROS-V

0000h

Powergood

Error Row (ERRROW):
This field holds the DRAM row (page) address of 

the read transaction that had the ECC error.

31:29

ROS-V

000b

Powergood

Error Bank Address (ERRBANK):

This field holds the Bank Address of the read 

transaction that had the ECC error.

28:27

ROS-V

00b

Powergood

Error Rank Address (ERRRANK):
This field holds the Rank ID of the read transaction 

that had the ECC error.

26:24

ROS-V

000b

Powergood

Error Chunk (ERRCHUNK):
Holds the chunk number of the error stored in the 

register.

23:16

ROS-V

00h

Powergood

Error Syndrome (ERRSYND):
This field contains the error syndrome. A value of FFh 

indicates that the error is due to poisoning.
For ERRSYND definition see 

15:2

RO

0h

Reserved (RSVD)