Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

20

Document Number: 327405

-

001

• Static lane numbering reversal

— Does not support dynamic lane reversal, as defined (optional) by the PCI 

Express Base Specification, Rev. 2.0.

• Supports Half Swing “low-power/low-voltage” mode.

The processor does not support PCI Express* Hot-Plug.

• DMI 2.0 support.
• Four lanes in each direction.
• 2.5 GT/s and 5.0 GT/s

 

DMI interface to PCH

• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per 

pair of 250 MB/s given the 8b/10b encoding used to transmit data across this 

interface. Does not account for packet overhead and link maintenance.

• Gen2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per 

pair of 500 MB/s given the 8b/10b encoding used to transmit data across this 

interface. Does not account for packet overhead and link maintenance.

• Maximum theoretical bandwidth on interface of 2 GB/s in each direction 

simultaneously, for an aggregate of 4 GB/s when DMI x4. 

• Shares 100-MHz PCI Express* reference clock.
• 64-bit downstream address format, but the processor never generates an address 

above 64 GB (Bits 63:36 will always be zeros).

• 64-bit upstream address format, but the processor responds to upstream read 

transactions to addresses above 64 GB (addresses where any of Bits 63:36 are 

nonzero) with an Unsupported Request response. Upstream write transactions to 

addresses above 64 GB will be dropped. 

• Supports the following traffic types to or from the PCH:

— DMI  ->  DRAM
— DMI -> processor core

(Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

— Processor core -> DMI

• APIC and MSI interrupt messaging support:

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI and SERR error indication.
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port 

DMA, floppy drive, and LPC bus masters.

• DC coupling – no capacitors between the processor and the PCH.
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage”.

The PECI is a one-wire interface that provides a communication channel between a 

PECI client (the processor) and a PECI master. The processors support the PECI 3.0 

Specification.