Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

40

Document Number: 327405

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001

• Virtual Processor IDs (VPID)

— Ability to assign a VM ID to tag processor core hardware structures (e.g., TLBs) 
— This avoids flushes on VM transitions to give a lower-cost VM transition time 

and an overall reduction in virtualization overhead.

• Guest Preemption Timer

— Mechanism for a VMM to preempt the execution of a guest OS after an amount 

of time specified by the VMM. The VMM sets a timer value before entering a 

guest

— The feature aids VMM developers in flexibility and Quality of Service (QoS) 

guarantees

• Descriptor-Table Exiting

— Descriptor-table exiting allows a VMM to protect a guest OS from internal 

(malicious software based) attack by preventing relocation of key system data 

structures like IDT (interrupt descriptor table), GDT (global descriptor table), 

LDT (local descriptor table), and TSS (task segment selector). 

— A VMM using this feature can intercept (by a VM exit) attempts to relocate 

these data structures and prevent them from being tampered by malicious 

software.

The key Intel

®

 VT-d objectives are domain-based isolation and hardware-based 

virtualization. A domain can be abstractly defined as an isolated environment in a 

platform to which a subset of host physical memory is allocated. Virtualization allows 

for the creation of one or more partitions on a single system. This could be multiple 

partitions in the same operating system, or there can be multiple operating system 

instances running on the same system, offering benefits like system consolidation, 

legacy migration, activity partitioning, or security.

The processor supports the following Intel

®

 VT-d features:

• Memory controller complies with Intel

®

 VT-d 1.2 specification. 

• Intel

®

 VT-d DMA remap engines.

— DMI (non-high def audio)
— PCI Express*

• Support for root entry, context entry and default context
• 39-bit guest physical address and host physical address widths
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support 

for MSI interrupts for faults

• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending 

reads, on IOTLB invalidation

• Support for page-selective IOTLB invalidation