Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

64

Document Number: 327405

-

001

• The voltage is optimized according to the temperature, the core bus ratio, and 

number of cores in deep C-states.

• The core power and temperature are reduced while minimizing performance 

degradation. 

A small amount of hysteresis has been included to prevent an excessive amount of 

operating point transitions when the processor temperature is near its maximum 

operating temperature. Once the temperature has dropped below the maximum 

operating temperature, the operating frequency and voltage transition back to the 

normal system operating point. This is illustrated in 

Once a target frequency/bus ratio is resolved, the processor core transitions to the new 

target automatically.

• On an upward operating point transition, the voltage transition precedes the 

frequency transition.

• On a downward transition, the frequency transition precedes the voltage transition.

When transitioning to a target core operating voltage, a new SVID code to the voltage 

regulator is issued. The voltage regulator must support dynamic SVID steps to support 

this method.

During the voltage change:

• It is necessary to transition through multiple SVID steps to reach the target 

operating voltage.

• Each step is 5 mV for Intel MVP-7.0 compliant VRs.
• The processor continues to execute instructions. However, the processor halts 

instruction execution for frequency transitions.