Техническая Спецификация для Intel E3-1105C AV8062701048800
Модели
AV8062701048800
Signal Description
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2
May 2012
72
Document Number: 327405
-
001
SA_CAS#
CAS Control Signal: Used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
DDR3
SA_DQS[7:0]
SA_DQS#[7:0]
Data Strobes: SA_DQS[7:0] and its complement
signal group make up a differential strobe pair.
The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS#[7:0] during read
and write transactions.
I/O
DDR3
SA_DQS[8]
SA_DQS#[8]
Data Strobes: SA_DQS[8] is the data strobe for
the ECC check data bits SA_DQ[71:64].
SA_DQS#[8] is the complement strobe for the
ECC check data bits SA_DQ[71:64]
The data is captured at the crossing point of
The data is captured at the crossing point of
SA_DQS[8:0] and its SA_DQS#[8:0] during read
and write transactions.
Note: Not required for non-ECC mode
Note: Not required for non-ECC mode
I/O
DDR3
SA_DQ[63:0]
Data Bus: Channel A data signal interface to the
SDRAM data bus.
I/O
DDR3
SA_ECC_CB[7:0]
ECC Data Lines: Data Lines for ECC Check Byte
for Channel A.
Note: Not required for non-ECC mode
Note: Not required for non-ECC mode
I/O
DDR3
SA_MA[15:0]
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
O
DDR3
SA_CK[3:0]
SA_CK#[3:0]
SDRAM Differential Clock: Channel A SDRAM
Differential clock signal pair. The crossing of the
positive edge of SA_CK and the negative edge of
its complement SA_CK# are used to sample the
command and control signals on the SDRAM.
O
DDR3
SA_CKE[3:0]
Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-
refresh during STR.
O
DDR3
SA_CS#[3:0]
Chip Select: (1 per rank) Used to select
particular SDRAM components during the active
state. There is one Chip Select for each SDRAM
rank.
O
DDR3
SA_ODT[3:0]
On Die Termination: Active Termination Control.
O
DDR3
Table 8-3.
Memory Channel B (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
SB_BS[2:0]
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O
DDR3
SB_WE#
Write Enable Control Signal: Used with
SB_RAS# and SB_CAS# (along with SB_CS#) to
define the SDRAM Commands.
O
DDR3
SB_RAS#
RAS Control Signal: Used with SB_CAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
O
DDR3
Table 8-2.
Memory Channel A (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type