Техническая Спецификация для Intel E3-1105C AV8062701048800
Модели
AV8062701048800
Signal Description
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2
May 2012
78
Document Number: 327405
-
001
8.9
Power Sequencing
8.10
Processor Power and Ground Signals
Table 8-11. Power Sequencing
Signal Name
Description
Direction/Buffer
Type
SM_DRAMPWROK
SM_DRAMPWROK Processor Input: Connects to
PCH DRAMPWROK.
I
Asynchronous
CMOS
UNCOREPWRGOOD
The processor requires this input signal to be a clean
indication that the VCCSA, VCCIO, VAXG, and VDDQ,
power supplies are stable and within specifications.
This requirement applies regardless of the S-state of
the processor. 'Clean' implies that the signal remains
low (capable of sinking leakage current), without
glitches, from the time that the power supplies are
turned on until they come within specification. The
signal must then transition monotonically to a high
state. This is connected to the PCH PROCPWRGD
signal.
I
Asynchronous
CMOS
PROC_DETECT#
PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this signal.
System board designers may use this signal to
determine if the processor is present.
Table 8-12. Processor Power Signals
Signal Name
Description
Direction/Buffer
Type
VCC
Processor core power rail.
PWR
VCCIO
Processor power for I/O
PWR
VDDQ
Processor I/O supply voltage for DDR3.
PWR
VCCPLL
VCCPLL provides isolated power for internal
processor PLLs.
PWR
VCCSA
System Agent power supply
PWR
VIDSOUT
VIDSCLK
VIDALERT#
VIDALERT#, VIDSCLK, and VIDSCLK comprise a
three signal serial synchronous interface used to
transfer power management information between
the processor and the voltage regulator controllers.
This serial VID (SVID) interface replaces the
parallel VID interface on previous processors.
I/O
O
I
CMOS
VCCSA_VID
Voltage selection for VCCSA: This pin must have
a pull down resistor to ground.
O
CMOS
VSS
Processor ground node
GND