Техническая Спецификация для Intel E3-1105C AV8062701048800

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

81

The processor has V

CC

, V

CCIO

, V

DDQ, 

V

CCPLL, 

V

CCSA

 and V

SS 

(ground) inputs for on-chip 

power distribution. All power pins must be connected to their respective processor 

power planes, while all V

SS

 pins must be connected to the system ground plane. Use of 

multiple power and ground planes is recommended to reduce I*R drop. The V

CC

 pins 

must be supplied with the voltage determined by the processor Serial Voltage 

IDentification (SVID) interface. 

 specifies the voltage level for the various 

VIDs. 

Due to its large number of transistors and high internal clock speeds, the processor is 

capable of generating large current swings between low- and full-power states. To keep 

voltages within specification, output decoupling must be properly designed.

Design the board to ensure that the voltage provided to the processor remains within 

the specifications listed in 

. Failure to do so can result in timing violations or 

reduced lifetime of the processor. 

The voltage regulator solution must:

• Provide sufficient decoupling to compensate for large current swings generated 

during different power mode transitions.

• Provide low parasitic resistance from the regulator to the socket.
• Meet voltage and current specifications as defined in 

.