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AV8063801058401

Datasheet, Volume 1



4.2.4

Core C-states ........................................................................................ 52
4.2.4.1

Core C0 State........................................................................... 52

4.2.4.2

Core C1 / C1E State .................................................................. 53

4.2.4.3

Core C3 State........................................................................... 53

4.2.4.4

Core C6 State........................................................................... 53

4.2.4.5

C-State Auto-Demotion ............................................................. 53

4.2.5

Package C-States ................................................................................... 54
4.2.5.1

Package C0 .............................................................................. 55

4.2.5.2

Package C1/C1E ....................................................................... 55

4.2.5.3

Package C3 State...................................................................... 56

4.2.5.4

Package C6 State...................................................................... 56

4.3

Integrated Memory Controller (IMC) Power Management ........................................ 56
4.3.1

Disabling Unused System Memory Outputs ................................................ 56

4.3.2

DRAM Power Management and Initialization ............................................... 57
4.3.2.1

Initialization Role of CKE............................................................ 58

4.3.2.2

Conditional Self-Refresh ............................................................ 58

4.3.2.3

Dynamic Power Down Operation ................................................. 59

4.3.2.4

DRAM I/O Power Management .................................................... 59

4.3.3

DDR Electrical Power Gating (EPG) ........................................................... 59

4.4

PCI Express* Power Management ........................................................................ 60

4.5

DMI Power Management..................................................................................... 60

4.6

Graphics Power Management .............................................................................. 60
4.6.1

Intel

Rapid Memory Power Management (Intel

RMPM) 

(also known as CxSR) ............................................................................. 60

4.6.2

Intel

Graphics Performance Modulation Technology (Intel

GPMT) .............. 60

4.6.3

Graphics Render C-State ......................................................................... 60

4.6.4

Intel

Smart 2D Display Technology (Intel

S2DDT) .................................. 61

4.6.5

Intel

Graphics Dynamic Frequency.......................................................... 61

4.7

Graphics Thermal Power Management .................................................................. 61

Thermal Management .............................................................................................. 63

Signal Description ................................................................................................... 65
6.1

System Memory Interface Signals........................................................................ 66

6.2

Memory Reference and Compensation Signals ....................................................... 67

6.3

Reset and Miscellaneous Signals.......................................................................... 68

6.4

PCI Express*-based Interface Signals .................................................................. 69

6.5

Intel

Flexible Display (Intel

FDI) Interface Signals ............................................. 69

6.6

Direct Media Interface (DMI) Signals.................................................................... 70

6.7

Phase Lock Loop (PLL) Signals ............................................................................ 70

6.8

Test Access Points (TAP) Signals ......................................................................... 70

6.9

Error and Thermal Protection Signals ................................................................... 71

Electrical Specifications ........................................................................................... 75
7.1

Power and Ground Lands.................................................................................... 75

7.2

Decoupling Guidelines........................................................................................ 75
7.2.1

Voltage Rail Decoupling........................................................................... 75

7.3

Processor Clocking (BCLK[0], BCLK#[0]) .............................................................. 76
7.3.1

Phase Lock Loop (PLL) Power Supply......................................................... 76

7.4

VCC Voltage Identification (VID).......................................................................... 76

7.5

System Agent (SA) V

VID................................................................................ 80

7.6

Reserved or Unused Signals................................................................................ 80