Техническая Спецификация для Intel D2500 DF8064101055400
Модели
DF8064101055400
Datasheet - Volume 1 of 2
107
7.2.6.5
C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM.Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
7.2.6.6
C-State Auto-Demotion
In general, deeper C-states such as C6 have long latencies and have higher energy
entry/exit costs. The resulting performance and energy penalties become significant
when the entry/exit frequency of a deeper C-state is high. Therefore incorrect or
inefficient usage of deeper C-states have a negative impact on battery life. In order to
increase residency and improve battery life in deeper C-states, the processor supports
C-state auto-demotion.
There are two C-State auto-demotion options:
•
C6 to C3
•
C6/C3 To C1
The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s
immediate residency history. Upon each core C6 request, the core C-state is demoted
to C3 or C1 until a sufficient amount of residency has been established. At that point, a
core is allowed to go into C3/C6. Each option can be run concurrently or individually.
This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
7.2.7
Package C-States
The processor supports C0, C1/C1E, C2/C2E, C4/C4E and C6 power states. The
following is a summary of the general rules for package C-state entry. These apply to
all package Cstates unless specified otherwise:
•
Package C-state request is determined by the lowest numerical core C-state
amongst all cores.
•
A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
•
Each core can be at a lower idle power state than the package if the platform does
not grant the processor permission to enter a requested package C-state.
•
The platform may allow additional power savings to be realized in the processor.
•
For package C-states, the processor is not required to enter C0 before entering any
other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
•
If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.