Техническая Спецификация для Intel G632 CM8062301049304

Voltage Range for

Processor Idle Mode

(Package C7 Plus)

All

1.3

—

—

Voltage Range for

Processor Idle Mode

(Package C8)

All

1.3

—

—

Voltage Range for

Processor Idle Mode

(Package C9-C10)

All

0

—

—

I

CCMAX

Maximum Processor Core

I

CC

Intel

®

 Core

™

 U-

Processor Line
28 W

—

—

40

A

4, 6, 7

Intel

®

 Core

™

U-Processor

Line
15 W

—

—

32

Intel

®

 Pentium

®

Processor
Intel

®

 Celeron

®

Processor

—

—

32

Intel

®

 Core

™

 M

Processor Family

—

—

18

TOL

VCC

Voltage

Tolerance

PS0, PS1

All

—

—

±20

mV

6, 8

PS2, PS3

—

—

±20

Ripple

Ripple

Tolerance

PS0

All

—

—

±15

mV

6, 8

PS1

—

—

±15

PS2

—

—

+50/-15

PS3

—

—

+60/-15

R_DC_LL

Loadline slope within the

VR regulation loop

capability

All

—

-2.0

—

mΩ

—

R_AC_LL

Loadline slope in

response to dynamic load

increase events

All

—

-7.0

—

mΩ

—

T_OVS_Max

Maximum Overshoot time

All

—

—

500

μs

—

V_OVS

Maximum Overshoot

All

—

—

200

mV

—

Notes: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data.

These specifications will be updated with characterized data from silicon measurements at a later date.

2. Each processor is programmed with a maximum valid voltage identification value (VID) that is set at manufacturing

and cannot be altered. Individual maximum VID values are calibrated during manufacturing such that two

processors at the same frequency may have different settings within the VID range. Note that this differs from the

VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel

SpeedStep Technology, or Low-Power States).

3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with

a 20 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The

maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is

not coupled into the oscilloscope probe.

4. Processor core VR to be designed to electrically support this current.
5. Processor core VR to be designed to thermally support this current indefinitely.
6. Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated.
7. Long term reliability cannot be assured in conditions above or below Maximum/Minimum functional limits.

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

Datasheet – Volume 1 of 2

March 2015

88

Order No.: 330834-004v1