Техническая Спецификация для Intel i5-4200H CL8064701470601

Enabled

Single

Any native resolution 

3

PC7

Enabled

Multiple

Any native resolution 

1

Same as PSR disabled for

the given resolution with

multiple displays

Notes: 1. For multiple display cases, the resolution listed is the highest native resolution of all enabled

displays, and PSR is internally disabled; that is, dual display with one 800x600 60 Hz display and

one 2560x1600 60 Hz display will result in a deepest available package C-state of PC2.

2. For non-native resolutions, PSR is internally disabled, and the deepest available package C-State

will be between that of the PSR disabled native resolution and the PSR disabled non-native

resolution; that is, a native 3200x1800 60 Hz panel using non-native 1920x1080 60 Hz

resolution will result in a deepest available package C-State between PC3 and PC6.

3. Microcode Update Revision 00000010 or newer must be used.

The main memory is power managed during normal operation and in low-power ACPI

Cx states.

Any system memory (SM) interface signal that goes to a memory module connector in

which it is not connected to any actual memory devices (such as SO-DIMM connector

is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM

signals are:
•

Reduced power consumption.

•

Reduced possible overshoot/undershoot signal quality issues seen by the

processor I/O buffer receivers caused by reflections from potentially un-

terminated transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are

not driven.

At reset, all rows must be assumed to be populated, until it can be determined that

the rows are not populated. This is due to the fact that when CKE is tri-stated with an

SO-DIMM present, the SO-DIMM is not ensured to maintain data integrity.

CKE tristate should be enabled by BIOS where appropriate, since at reset all rows

must be assumed to be populated.

The processor implements extensive support for power management on the SDRAM

interface. There are four SDRAM operations associated with the Clock Enable (CKE)

signals, which the SDRAM controller supports. The processor drives four CKE pins to

perform these operations.

The CKE is one of the power-save means. When CKE is off, the internal DDR clock is

disabled and the DDR power is reduced. The power-saving differs according to the

selected mode and the DDR type used. For more information, refer to the IDD table in

the DDR specification.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 328901-007

63