Техническая Спецификация для Intel i5-4200H CL8064701470601

SM_RCOMP[2:0]

I

A

SM_VREF

DDR3L Reference Voltage: This signal is used as a

reference voltage to the DDR3L/DDR3L-RS controller and

is defined as V

DDQ

/2.

O

DDR3L/DDR3L-RS

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

The output pins are connected to the DIMMs, and holds

V

DDQ

/2 as reference voltage.

O

DDR3L

/DDR3L-RS

CFG[19:0]

Configuration Signals: The CFG signals have a default value of

'1' if not terminated on the board.
• CFG[1:0]: Reserved configuration lane. A test point may be

placed on the board for these lanes.

• CFG[2]: PCI Express* Static x16 Lane Numbering Reversal.

— 1 = Normal operation
— 0 = Lane numbers reversed.

• CFG[3]: MSR Privacy Bit Feature

— 1 = Debug capability is determined by

IA32_Debug_Interface_MSR (C80h) bit[0] setting

— 0 = IA32_Debug_Interface_MSR (C80h) bit[0] default

setting overridden

• CFG[4]: eDP enable

— 1 = Disabled
— 0 = Enabled

• CFG[6:5]: PCI Express* Bifurcation:

— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*

• CFG[19:7]: Reserved configuration lanes. A test point may

be placed on the board for these lands.

I/O

GTL

CFG_RCOMP

Configuration resistance compensation. Use a 49.9 Ω ±1%

resistor to ground.

—

FC_x

FC (Future Compatibility) signals are signals that are available for

compatibility with other processors. A test point may be placed

on the board for these lands.

PM_SYNC

Power Management Sync: A sideband signal to communicate

power management status from the platform to the processor.

I

CMOS

PWR_DEBUG#

Signal is for debug.

I

Asynchronous

CMOS

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

86

Order No.: 328901-007