Техническая Спецификация для Intel C2550 FH8065401488912
Модели
FH8065401488912
Volume 2—Serial Peripheral Interface (SPI)—C2000 Product Family
Flash Descriptor
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
478
Order Number: 330061-002US
22.5.1
Master Section
The master section defines the read and write access setting for each region of the SPI
device when the SPI controller is running in a descriptor mode. The master region
recognizes only one master: the CPU core running the BIOS code.
22.5.2
Invalid Flash Descriptor Handling
The SoC responds to an invalid Flash Descriptor with the following:
• The SPI controller operates in the non-descriptor mode.
• If the BBS strap is set to 1, the BIOS direct read access is forwarded to the SPI
• If the BBS strap is set to 1, the BIOS direct read access is forwarded to the SPI
controller without any address translation. See
for BBS details.
• All security checks are disabled and the entire Flash is open for reading and writing.
No restriction is on the 4k crossing.
Note:
To ensure BIOS boot access even when the Flash Descriptor is invalid, the BIOS region
is placed at the top of Flash component 0. Placing the BIOS region in any other location
necessitates a full reprogramming of the Flash before a boot occurs from that Flash.
22.5.3
Descriptor Security Override Strap
/GPIOS_7 pin (AH50) to allow the descriptor
security to be overridden when the strap is sampled low.
If the strap is set (0b), it has the following effect:
• The master region read access and master region write access permissions that
were loaded from the Flash Descriptor master section are overridden, giving every
master read and write permissions to the entire Flash component including areas
outside the defined regions.
• The BIOS Protected Range 4 (PR4), if enabled by a soft strap, is overridden so that
all masters are able to write to the PR4. The PR4 base and limit addresses are
fetched and received from a soft strap.