Техническая Спецификация для Intel C2518 FH8065501516710
Модели
FH8065501516710
Volume 2—Power Management—C2000 Product Family
Processor Power States - C-States
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
164
Order Number: 330061-002US
Module C-States (designated as MC) pertain to the two-core CMP module while the
Core C-States (designated as CC) independently pertain to each of the two cores within
the CMP. Package C-States (designated as PC) pertain to the entire set of CMP modules
available in the particular product SKU.
The C-State characteristics for the Silvermont processor are different than previous
Intel
®
Atom
TM
processors. Most changes involve the C6 and the new C6C state. The
SoC core C6 state does not provide flushing of dirty data from the L2 cache.
Note:
C1E cannot be disabled because it is required for reliability purposes. This means that
when all the cores are idle for a period of time, the SoC will lower the frequency to the
low frequency mode, particularly if C6 is disabled.
Table 9-8.
Core C-States
General
C-State
Core
C-State
Description
C0
C0
Active State
C1
CC1
Some core clocks gated.
L1 Data Cache Snoops are serviced.
C6
CC6-NS
• Cores are placed in LFM (based on Energy Perf Bias Setting)
• Core power gated and clock gated
• L1 Data cache is flushed
• Core power gated and clock gated
• L1 Data cache is flushed
The NS hints from the software.
Table 9-9.
Module C-States
General
C-State
CMP
Module
C-State
Core Status
L1 and L2 Cache Status
C0
MC0
At least one core in C0 state
Normal L1 and L2 cache operation
C1
MC1
Both cores HALTed
Most clocks off
No cache flushed
Cache Snoops wake-up cores
C6
MC0
Both cores are in the C6 (powered-off) state.
VID is determined at a package level not
module level.
CPU reference clock off
Core L1 data cache flushed
Four of 16 ways of L2 cache retained
Table 9-10. Package C-States
General
C-State
CMP
Package
C-State
When Entered
C0
PC0
When in PC4, PC6, or PC7, one of the following occurs:
• MSI Break
• Snoop Wake
• Machine Check Error
• Always-On Timer (AONT) expires in one of the cores
• Snoop Wake
• Machine Check Error
• Always-On Timer (AONT) expires in one of the cores
Various actions are taken by the SoC once the PC0 state is entered.
C1
PC1
When all cores are in C1 and based on the overall C6 residency, the frequency will be
lowered to a value between LFM and Guaranteed.