Техническая Спецификация для Intel C2518 FH8065501516710
Модели
FH8065501516710
Volume 2—Memory Controller—C2000 Product Family
RAS Features
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
62
Order Number: 330061-002US
3.4.3
Demand and Patrol Scrubbing
Demand scrub is an operation when a read request encounters a correctable memory
error and the read data is corrected (scrubbed) and written back to memory. Without
demand scrub the corrected data is only delivered to the requester and the corrupted
data is still left in memory. Demand scrub fixes the error in memory when it is
detected, thus lowering the probability that a second error to the same 8B memory
location would change the correctable error into an uncorrectable error.
When a correctable error is detected, the SoC integrated memory controller returns the
corrected read data to the internal SoC buffer along with a correctable error
notification. The buffer logic then marks the data buffer that receives the read data as
dirty (modified), which causes an eventual writeback to memory. When the writeback
occurs, the previously-corrected read data is written back to memory with the correct
ECC, thus scrubbing the memory location before it can be read again. Demand scrub is
only employed for fixing correctable ECC errors from a read to physical DRAM and
should exclude MMIO access.
Patrol scrub is a method in which the cleanup process is initiated in the background by
the internal SoC memory buffer. When patrol scrub is enabled, the buffer reads all of
memory locations starting at Address 0, Rank 0 at a very low bandwidth for the
purpose of fixing correctable errors. The patrol scrub agent issues read requests and
does nothing with the read data (silently dropped). When a correctable error is
detected, the memory controller performs the update and writes the modified data
back to memory.
The BDPSCRUB (BDPSCRUB)—Offset 17Ah SoC sideband register is used to enable the
patrol scrub engine. The BDPSCRUB register is also used to set the scrub period for the
desired scrub rate. At the default scrub period, 8 GB of memory can be scrubbed in
about 24 hours. The scrubbing process skips the low MMIO region and the upper bound
is dictated by the amount of memory installed. Software is also provided the ability to
set the start of the scrub address in the BDPSADDR (BDPSADDR)—Offset 17Bh SoC
sideband register. Note that the scrub engine operates at the lowest priority level,
which will not cause the memory to exit self-refresh.
Note:
Additionally, the scrub engine does not ensure that the scrubs are issued at the
specified rate; the specified rate is only the maximum rate. The scrub timer is ignored
if the patrol scrub engine is waiting to issue a scrub request.
3.4.4
DDR3 Data Scrambling
Data scrambling is a technique to reduce supply noise and improve DRAM data signal
integrity by XORing data bits and ECC bits in a pseudo random sequence. The pseudo
random sequence has two important effects relative to power delivery. Across the
72 data/ECC bits of the bus, this feature ensures approximately 50% of the bits are
logical 1 and the other 50% are logical 0 in every cycle. This eliminates the previous
worst case where all bus bits simultaneously drive high or low. The second benefit of
scrambling produces a white spectrum eliminating data dependent resonance patterns.
If these resonance patterns hit the correct frequency relative to the LC tank circuits in
the power delivery network, they create significant amounts of supply noise. In terms
of signal integrity, the worst case margin is empirically found when a large number of
bits transitioning in a specific fashion to create the worst case ISI, crosstalk and supply
noise simultaneously on a given victim bit. Data scrambling makes it unlikely that all
these bits switch in the correct fashion, hitting these worst-case patterns.
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