Техническая Спецификация для Intel C2350 FH8065401488914
Модели
FH8065401488914
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
311
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Block Write
(1 byte)
1
0
2
0
0
Valid and points to
2 bytes (command
and 1-data byte);
the byte count is
calculated by the
hardware.
X
Block Write
(2 bytes)
1
0
3
0
0
Valid and points to
3 bytes (command
and 2-data bytes);
the byte count is
calculated by the
hardware.
X
Block Write
(3 bytes or
more)
1
0
4 or more
1
0
0
Valid and points to
at least 4 bytes
(command and 3-
data bytes); the
byte count is
calculated by the
hardware.
X
Block Read
(1 byte)
1
1
Command
2
1
X
Valid and points to
a buffer where the
received 2 bytes
are placed (byte
count, data byte 1).
Block Read
(2 bytes or
more)
1
Command
3 or
more
2
1
X
Valid and points to
a buffer where at
least the received
3 bytes are placed
(byte count, data
byte 1, etc.).
Block Write-
Block Read
Process
Call
3
(write
1 byte, read
N)
1
0
2
N
4
+1
1
Valid and points to
2 bytes (command
and 1-data byte);
the byte count is
calculated by the
hardware.
Valid and points to
a buffer where at
least the received
(N+1) bytes are
placed (byte count,
N data bytes).
Block Write-
Block Read
Process Call
(write
2 bytes,
read N)
1
0
3
N+1
1
Valid and points to
3 bytes (command
and 2-data bytes);
the byte count is
calculated by the
hardware.
Valid and points to
a buffer where at
least the received
(N+1) bytes are
placed (byte count,
N data bytes).
Block Write-
Block Read
Process Call
(write
>2 bytes,
read N)
1
0
4 or more
N+1
1
Valid and points to
at least 4 bytes
(command and
3-data bytes); the
byte count is
calculated by the
hardware.
Valid and points to
a buffer where at
least the received
(N+1) bytes are
placed (byte count,
N data bytes).
1. Per the System Management Bus (SMBus) Specification, Version 2.0, having a block write of exactly 3 bytes
can occur. However, a block write of 3 bytes and a write word have identical signaling on the bus.
2. Per the SMBus 2.0 Specification, having a block read of exactly 2 bytes can occur. However, a block read of
1-data byte (address, command, byte count = 1, followed by 1-data byte) and a read word from the target
(address, command, DataByte1, DataByte2) have identical signaling on the bus.
3. The sum of the data bytes in the write and read phases must not exceed 32 bytes per the SMBus 2.0
Specification.
4. N must be greater than 1.
Table 15-14. SMBus Transaction Encodings (Sheet 2 of 2)
SMBus
Command
BLK
C/
WRL
WRLNTH
RDLNTH
RW
(0=W;
1=R)
DPTR
(Points to TX
Data)
DPTR
(Points to RX
Data)