Техническая Спецификация для Intel E3845 FH8065301487715
Модели
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4231
27.8.2
Divisor Latch (High)/ Interrupt Enable Register. (IER_DLH)—
Offset 4h
Register bits [7:0] is used for different purposes depending on the mode. DLH (Divisor
Latch High) Upper 8-bits of a 16-bit, read/write, Divisor Latch register that contains the
baud rate divisor for the UART. This register may be accessed only when the DLAB bit
(LCR[7]) is set. The output baud rate is equal to the serial clock frequency divided by
sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock
freq) / (16 * divisor). Note that with the Divisor Latch Registers (DLL and DLH) set to
zero, the baud clock is disabled and no serial communications occur. Also, once the DLH
is set, at least 8 clock cycles of the slowest HSUart clock should be allowed to pass
before transmitting or receiving data.
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:8
0b
RO
RSVD0:
Reserved
7:0
0h
RW
rbr_thr_dll:
RBR[7:0] (Receive Buffer Register) (Read Only):
Data byte received on the serial input port (sin) in UART mode. The data in this register
is valid only if the Data Ready (DR) bit in the Line Status Register (LCR) is set.
If FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the
next data arrives, otherwise it is overwritten, resulting in an over-run error.
If FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive
FIFO. If the receive FIFO is full and this register is not read before the next data
character arrives, then the data already in the FIFO is preserved, but any incoming data
are lost and an over-run error occurs.
THR[7:0] (Transmit Holding Register) (Write Only):
Data to be transmitted on the serial output port (sout) in UART mode. Data should only
be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set.
If in non-FIFO mode or FIFOs are disabled (FCR[0] = 0) and THRE is set, writing a single
character to the THR clears the THRE. Any additional writes to the THR before the THRE
is set again causes the THR data to be overwritten.
If in FIFO mode and FIFOs are enabled (FCR[0] = 1) and THRE is set, x number of
characters of data may be written to the THR before the FIFO is full. The number x
(default=16) is determined by the value of FIFO Depth that you set during
configuration. Any attempt to write data when the FIFO is full results in the write data
being lost.
DLL[7:0] (Divisor Latch Low) (Read-Write):
Lower 8 bits of a 16-bit, read/write, Divisor Latch register that contains the baud rate
divisor for the UART. this register may be accessed only when the DLAB bit (LCR[7]) is
set.
The output baud rate is equal to the serial frequency divided by sixteen times the value
of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor).
Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is
disabled and no serial communications occur. Also, once the DLL is set, at least 8 clock
cycles of the slowest HSUart clock should be allowed to pass before transmitting or
receiving data.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:30, F:3] + 10h