Техническая Спецификация для Intel E3845 FH8065301487715

Intel

®

 Atom™ Processor E3800 Product Family

4350

Datasheet

14

0b

RW

This bit is 

set by hardware to indicate that the system woke due to a PCI Express wakeup event. 

This event can be caused by the PCI Express WAKE# pins (PMU_WAKE_B, 

PCI_WAKE1_B, PCI_WAKE2_B, PCI_WAKE3_B) being active, or one or more of the PCI 

Express ports being in beacon state, or recept of a PCI Express PME message at root 

port. This bit should only be set when one of these events causes the system to 

transition from a non-S0 system power state to the S0 system power state. This bit is 

set independant of the PCIEXP_WAKE_DIS bit. Software writes a 1 to clear this bit. If 

one of the WAKE# pins is still active during the write or one or more PCI Express ports 

is in the beacon state or PME message received indication is not cleared in the root port, 

then the bit will remain Power Management active (i.e. all inputs to this bit are level 

sensitive) Note: This bit does not itself cause a wake event or prevent entry to a 

sleeping state. Thus if the bit is 1 and the system is put into a sleeping state, the system 

will not auatomatically wake. reset_type=pmc_global_rst_b

13

0b

RW

This bit is 

set by hardware to indicate that the system woke due to change in USB serial lines. This 

bit is set independant of the USB_CLKLESS_EN bit. Software writes a 1 to clear this bit. 

reset_type=pmc_global_rst_b

12

0b

RO

Reserved.

11

0b

RW

This bit is set any 

time a Power Button Override Event occurs (i.e. the power button is pressed for at least 

4 consecutive seconds), or due to an internal thermal sensor catastrophic condition. 

These events cause an unconditional transition to the S5 state. The BIOS or SCI handler 

clears this bit by writing a 1 to it. This bit is not affected by hard resets via CF9h writes, 

and is not reset by RSMRST_B. Thus, this bit is preserved through power failures. Note 

that this bit is still asserted when the global SCI_EN is set to '1' then an SCI will be 

generated. reset_type=SRTCRST_B

10

0b

RW

This bit is set when the RTC generates an alarm 

(assertion of the IRQ8# signal), and is not affected by any other enable bit. See RTC_EN 

for the effect when RTC_STS goes active. This bit is only set by hardware and can only 

be reset by writing a one to this bit position. This bit is not affected by hard resets 

caused by a CF9 write, but is reset by RSMRST_B. reset_type=RSMRST_B

9

0b

RO

Reserved.

8

0b

RW

This bit is set when the 

PMU_PWRBTN_B signal is asserted (low), independent of any other enable bit. See 

PWRBTN_EN for the effect when PWRBTN_STS goes active. PWRBTN_STS is always a 

wake event. This bit is only set by hardware and can be cleared by software writing a 

one to this bit position. This bit is not affected by hard resets caused by a CF9 write, but 

is reset by RSMRST_B. If the PMU_PWRBTN_B signal is held low for more than 4 

seconds, the PMC clears the PWRBTN_STS bit, sets the PWRBTNOR_STS bit, the system 

transitions to the S5 state, and only PMU_PWRBTN_B is enabled as a wake event. If 

PWRBTN_STS bit is cleared by software while the PMU_PWRBTN_B pin is still held low, 

this will not cause the PWRBTN_STS bit to be set. The PMU_PWRBTN_B signal must go 

inactive and active again to set the PWRBTN_STS bit. Note that the CPU Thermal Trip 

and the Internal Thermal Sensors' Catastrophic Condition result in behavior matching 

the Powerbutton Override, which includes clearing this bit. reset_type=RSMRST_B

7:6

0b

RO

Reserved.

5

0b

RW

This bit is set when an SCI is generated due to the 

BIOS wanting the attention of the SCI handler. BIOS has a corresponding bit, 

BIOS_RLS, which will cause an SCI and set this bit. The SCI handler should then clear 

this bit by writing a 1 to it. This bit will not cause wake events or SMI#. This bit is not 

effected by SCI_EN. Note: GBL_STS being set will cause an SCI, even if the SCI_EN bit 

is not set. Software must take great care not to set the BIOS_RLS bit (which causes 

GBL_STS to be set) if the SCI handler is not in place. reset_type=PMU_PLTRST_B

4:1

0b

RO

reserved