Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
668
Datasheet
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RE
SE
RVED
DISPLA
Y
P
OR
T_HDMIB_HO
T
_
P
LUG_INP
UT_BUFFE
R_
LI
VE_ST
A
TE
DI
S
PLA
YP
OR
T
_
HDM
IC
_
HO
T
_
PLU
G
_INP
UT_BUFFE
R_
LI
VE_ST
A
TE
DISP
LA
Y
POR
T
D
_HO
T
_P
LUG_INP
U
T_BUFFE
R_
LI
VE_ST
A
TE
RESE
RVED
_1
PIPE_B_AUDIO_INTE
RRUP
T
_
LIVE_ST
A
T
E
DISPLA
YPOR
T_D_H
O
T_PLUG_INTE
RRUPT
_
D
ETE
C
T
_
ST
A
T
US
D
ISP
LA
YPO
R
T_
C
_
HO
T
_
PL
UG
_
IN
T
ER
R
U
P
T
_
D
E
T
EC
T_
S
TA
T
US
DISPLA
YPO
R
T_B_H
O
T_PLUG_INTE
RRUPT
_
D
ETE
C
T
_
ST
A
T
US
PIPE_A_AUDIO_INTE
RRUP
T
_
LIVE_ST
A
T
E
DIGIT
A
L_POR
T
_B_AUDIO_RE
Q
UEST
_
LIVE_ST
A
T
E
D
IG
IT
A
L_POR
T
_
C
_AUDIO_RE
Q
UEST
_
LIVE_ST
A
T
E
RESE
RVED
_2
CR
T_H
O
T_PLUG_INTE
RRUPT
_ST
A
TUS
TV_HO
T
_PLUG
_
INTE
RRUP
T
_ST
A
TUS
RESE
RVED
_3
RESE
RVED
_4
D
ISP
LA
YP
OR
T_
D_A
U
X
_
INT
E
R
R
U
P
T
_S
TA
T
U
S
DISP
LA
YP
OR
T_C
_
AU
X_
INTE
RRUPT
_ST
A
TUS
DIS
P
LA
Y
POR
T
_
B_AUX_INTE
RRUPT
_ST
A
TUS
SDVO_C
_HO
T
_PLUG
_
INTE
RRUP
T
_
D
ETE
C
T
_
ST
A
T
US
SD
VO_B_HO
T
_PLUG
_
INTE
RRUP
T
_
D
ETE
C
T
_
ST
A
T
US
PIPE_A_AUDIO_INTE
RRUP
T
_
D
ETE
C
T
_
ST
A
T
US
PIPE_B_AUDIO_INTE
RRUP
T
_
D
ETE
C
T
_
ST
A
T
US
Bit
Range
Default &
Access
Field Name (ID): Description
31:30
0b
RW
RESERVED:
mbz
29
0b
RO
DISPLAYPORT_HDMIB_HOT_PLUG_INPUT_BUFFER_LIVE_STATE:
[DevCDV,
DevCTG, DevELK] This bit is read-only. It reflects the real-time state of the of the hot
plug input (HPD pin) on DisplayPort or HDMI B when bit 29 of the hotplug enable
register, offset 61110h is set. This pin signal is active high. This does not feed into the
first line interrupt status register. This bit should be read to confirm cable connection
prior to attempting EDID read.
1 = HPD detected active
0 = HPD detected inactive
AccessType: Read Only
28
0b
RO
DISPLAYPORT_HDMIC_HOT_PLUG_INPUT_BUFFER_LIVE_STATE:
[DevCDV,
DevCTG, DevELK] This bit is read-only. It reflects the real-time state of the of the hot
plug input (HPD pin) on DisplayPortC when bit of this register is set. This pin signal is
active high. This does not feed into the first line interrupt status register. This bit should
be read to confirm cable connection prior to attempting EDID read.
1 = HPD detected high
0 = HPD detected low
AccessType: Read Only
27
0b
RO
DISPLAYPORTD_HOT_PLUG_INPUT_BUFFER_LIVE_STATE:
[DevCTG] This bit is
read-only. It reflects the real-time state of the of the hot plug input (HPD pin) on
DisplayPortD when bit of this register is set. This pin signal is active high. This does not
feed into the first line interrupt status register. Please note that port D is intended for
LFP use and therefore HPD may not be present. Bit 2 of the DPD control register must
therefore be read to determine whether DPD is used in the system.
1 = HPD detected high
0 = HPD detected low
AccessType: Read Only
26:24
0b
RW
RESERVED_1:
mbz