Техническая Спецификация для Intel E3815 FH8065301567411
Модели
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
717
Default: 00000000h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IM
A
G
E_ENH
A
NCE
M
ENT_H
IST
OG
RAM_E
N
A
B
LED
IMAG
E_E
N
HANC
EME
N
T
_
M
O
DIFIC
A
TION_T
A
B
LE_E
NA
BLED
R
E
S
E
R
V
E
D
_M
B
Z
_IM
A
G
E
_E
NH
ANC
E
ME
NT
_PIP
E_ASSIG
N
ME
NT
RE
SE
RVED
H
IST
OGRAM_MODE_SELE
C
T
SYNC_T
O_PHASE_IN_C
O
U
N
T
RESE
RVED
_1
ENH
A
N
C
EM
ENT
_
M
O
D
E
SY
NC_T
O
_
PH
AS
E_IN
BIN_REGISTE
R
_FU
N
CTIO
N
_
S
E
LE
CT
RESE
RVED
_2
B
IN_REG
ISTER_INDEX_READ_ONL
Y
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
IMAGE_ENHANCEMENT_HISTOGRAM_ENABLED:
This bit enables the Image
Enhancement histogram logic to collect data.
0 = Image histogram is disabled
1 = The Image histogram is enabled. When this bit is changed from a zero to a one,
histogram calculations will begin after the next VBLANK of the assigned pipe.
30
0b
RW
IMAGE_ENHANCEMENT_MODIFICATION_TABLE_ENABLED:
This bit enables the
Image Enhancement modification table.
0 = disabled
1 = enabled. When this bit is changed from a zero to a one, modifications begin after
the next VBLANK of the assigned pipe.
29
0b
RW
RESERVED_MBZ_IMAGE_ENHANCEMENT_PIPE_ASSIGNMENT:
Each pipe has its
own dedicated IE function.
28:25
0b
RW
RESERVED:
Always write as 0 s.
24
0b
RW
HISTOGRAM_MODE_SELECT:
0: YUV Luma Mode
1: HSV Intensity Mode - Reserved on [DevCL]
23:16
0b
RW
SYNC_TO_PHASE_IN_COUNT:
This field indicates the phase in count number on
which the Image Enhancement table will be loaded if the Sync to Phase in is enabled.
15
0b
RW
RESERVED_1:
Always write as 0.
14:13
0b
RW
ENHANCEMENT_MODE:
00: Direct look up mode
01: Additive mode
10: Multiplicative mode - Reserved on [DevCL]
11: Reserved
12
0b
RW
SYNC_TO_PHASE_IN:
Setting this bit enables the double buffered registers to be
loaded on the phase in count value specified instead of the next vblank.