Техническая Спецификация для Intel N2820 FH8065301616603
Модели
FH8065301616603
Datasheet
709
Low Power Engine (LPE) for Audio (I
2
S)
Programmed I/O can transfer data between:
•
The LPE core and the FIFO Data register for the TXFIFO
•
The processor Core and the FIFO Data register for the TXFIFO
•
The LPE core and the FIFO Data register for the RXFIFO
•
The processor Core and the FIFO Data register for the RXFIFO
•
The processor Core and the control or status registers
•
The LPE core and the control or status registers
DMA bursts can transfer data between:
•
Universal memory and the FIFO Data register for the TXFIFO
•
Universal memory and the FIFO Data register for the RXFIFO
•
Universal memory and the sequentially addressed control or status registers
16.6.4
LPE and DMA FIFO Access
The LPE or DMA access data through the Enhanced SSP Port’s Transmit and Receive
FIFOs. An LPE access takes the form of programmed I/O, transferring one FIFO entry
per access. LPE accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. LPE Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). LPE Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2 or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral).The DMA’s width register must be at least the SSP data size programmed
into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-bit location by
the processor. For Writes, the Enhanced SSP port takes the data from the Transmit
FIFO, serializes it, and sends it over the serial wire (I2S[2:0]_DATAOUT) to the external
peripheral. Receive data from the external peripheral (on I2S[2:0]_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
FIFOs. An LPE access takes the form of programmed I/O, transferring one FIFO entry
per access. LPE accesses would normally be triggered off of an SSSR Interrupt and
must always be 32 bits wide. LPE Writes to the FIFOs are 32 bits wide, but the
serializing logic will ignore all bits beyond the programmed FIFO data size (EDSS/DSS
value). LPE Reads to the FIFOs are also 32 bits wide, but the Receive data written into
the RX FIFO (from the RXD line) is stored with zeroes in the MSBs down to the
programmed data size. The FIFOs can also be accessed by DMA bursts, which must be
in multiples of 1, 2 or 4 bytes, depending upon the EDSS value, and must also transfer
one FIFO entry per access. When the SSCR0.EDSS bit is set, DMA bursts must be in
multiples of 4 bytes (the DMA must have the Enhanced SSP configured as a 32-bit
peripheral).The DMA’s width register must be at least the SSP data size programmed
into the SSP control registers EDSS and DSS. The FIFO is seen as one 32-bit location by
the processor. For Writes, the Enhanced SSP port takes the data from the Transmit
FIFO, serializes it, and sends it over the serial wire (I2S[2:0]_DATAOUT) to the external
peripheral. Receive data from the external peripheral (on I2S[2:0]_DATAIN) is
converted to parallel words and stored in the Receive FIFO.
A programmable FIFO trigger threshold, when exceeded, generates an Interrupt or
DMA service request that, if enabled, signals the CPU or DMA respectively to empty the
Receive FIFO or to refill the Transmit FIFO.
DMA service request that, if enabled, signals the CPU or DMA respectively to empty the
Receive FIFO or to refill the Transmit FIFO.
The Transmit and Receive FIFOs are differentiated by whether the access is a Read or a
Write transfer. Reads automatically target the Receive FIFO, while Writes will write data
to the Transmit FIFO. From a memory-map perspective, they are at the same address.
FIFOs are 16 samples deep by 32 bits wide. Each read or write is to 1 SSP sample.
Write transfer. Reads automatically target the Receive FIFO, while Writes will write data
to the Transmit FIFO. From a memory-map perspective, they are at the same address.
FIFOs are 16 samples deep by 32 bits wide. Each read or write is to 1 SSP sample.