Техническая Спецификация для Intel N2820 FH8065301616603
Модели
FH8065301616603
Datasheet
715
Low Power Engine (LPE) for Audio (I
2
S)
In full-duplex formats where the Enhanced SSP always receives the same number of
data samples as it transmits, the DMA should be set up to transmit and receive the
same number of bytes.
data samples as it transmits, the DMA should be set up to transmit and receive the
same number of bytes.
Note:
A TFT value of 0 means that there is one sample left in the TX FIFO.
Because the Enhanced SSP is not flow controlled, software must program the TX FIFO
Threshold (TFT), RX FIFO Threshold (RFT), and the DMA burst size to ensure that a TX
FIFO overflow or RX FIFO underflow does not occur. Software must also ensure that the
Enhanced SSP DMA requests are properly prioritized in the system to prevent fatal
overruns and under-runs.
Threshold (TFT), RX FIFO Threshold (RFT), and the DMA burst size to ensure that a TX
FIFO overflow or RX FIFO underflow does not occur. Software must also ensure that the
Enhanced SSP DMA requests are properly prioritized in the system to prevent fatal
overruns and under-runs.
The programming model for using the DMA is as follows:
•
Program the total number of Transmit/Receive byte lengths, DMA burst, and DMA
Width in the DMA.
Width in the DMA.
•
Set the preferred values in the Enhanced SSP Control registers.
•
Enable the Enhanced SSP by setting SSCR0.SSE.
•
Set the run bit in DMA Command Register.
•
The DMA will wait for either the Transmit or Receive Service requests.
•
If the Transmit/Receive byte length is not an even multiple of the transfer burst
size, a trailing byte condition may occur.
size, a trailing byte condition may occur.
16.7.2
Trailing Bytes in the Receive FIFO
When the number of samples in the Receive FIFO is less than its FIFO trigger threshold
level, and no additional data is received, the remaining bytes are called trailing bytes.
Trailing bytes can be handled by either the DMA or the processor, as indicated by the
SSCR1.TRAIL bit. Trailing bytes are identified by means of a timeout mechanism and
the existence of data within the Receive FIFO.
level, and no additional data is received, the remaining bytes are called trailing bytes.
Trailing bytes can be handled by either the DMA or the processor, as indicated by the
SSCR1.TRAIL bit. Trailing bytes are identified by means of a timeout mechanism and
the existence of data within the Receive FIFO.
16.7.2.1
Timeout
A timeout condition exists when the Receive FIFO has been idle for a period of time (in
APB clocks) defined by the value programmed within the Timeout register (SSTO).
When a timeout occurs, the receiver timeout interrupt SSSR.TINT bit will be set to a 1,
and if the Timeout Interrupt is enabled SSCR1.TINTE=1, a Timeout Interrupt will occur
to signal the processor that a timeout condition has occurred. The timeout timer is
reset after a new sample is received. Once the SSSR.TINT bit is set it must be cleared
by software by writing a 1 to it. Clearing this bit also causes the Timeout Interrupt, if
enabled, to be de-asserted.
APB clocks) defined by the value programmed within the Timeout register (SSTO).
When a timeout occurs, the receiver timeout interrupt SSSR.TINT bit will be set to a 1,
and if the Timeout Interrupt is enabled SSCR1.TINTE=1, a Timeout Interrupt will occur
to signal the processor that a timeout condition has occurred. The timeout timer is
reset after a new sample is received. Once the SSSR.TINT bit is set it must be cleared
by software by writing a 1 to it. Clearing this bit also causes the Timeout Interrupt, if
enabled, to be de-asserted.