Инструкции Пользователя для Biostar M7VIW BIOS
M7VIW BIOS Setup
16
PCI1 Post Write
When Enabled, CPU writes are allowed to post on the PCI bus.
The Choices: Enabled (default), Disabled.
PCI2 Post Write
When Enabled, CPU writes are allowed to post on the AGP bus.
The Choices: Enabled (default), Disabled.
The Choices: Enabled (default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI specification.
The Choices: Enabled (default), Disabled.
transactions cycles. Select Enabled to support compliance with PCI specification.
The Choices: Enabled (default), Disabled.
Memory Hole
When enabled, you can reserve an area of system memory for ISA adapter ROM. When
this area is reserved, it cannot be cached. Refer to the user documentation of the peripheral
you are installing for more information.
this area is reserved, it cannot be cached. Refer to the user documentation of the peripheral
you are installing for more information.
The Choices: Disabled (default), 15M – 16M.
System BIOS Cacheable
Selecting the “Enabled” option allows caching of the system BIOS ROM at
F0000h-FFFFFh, which can improve system performance. However, any programs writing
to this area of memory will cause conflicts and result in system errors.
F0000h-FFFFFh, which can improve system performance. However, any programs writing
to this area of memory will cause conflicts and result in system errors.
The Choices: Enabled, Disabled (default).
Video RAM Cacheable
Enabling this option allows caching of the video RAM, resulting a better system
performance. However, if any program writes to this memory area, a system error may
result.
performance. However, if any program writes to this memory area, a system error may
result.
The Choices: Disabled (default), Enabled.