Справочник Пользователя для Infineon 1024MB, 800MHz, DDR II, PC6400, CL6 HYS64T128000EU-2.5C2
Модели
HYS64T128000EU-2.5C2
HYS[64/72]T512020EU–[25F/2.5/3S]–A
Unbuffered DDR2 SDRAM Modules
Internet Data Sheet
Rev. 1.0, 2008-06
21
06112008-YHWK-B105
30) A maximum of eight Refresh commands can be posted to any given DDR2 SDRAM, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 9 x
t
REFI
.
31)
t
RPST
end point and
t
RPRE
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(
t
RPST
), or begins driving (
t
RPRE
shows a method to calculate these points when the device is no longer driving (
t
RPST
), or begins
driving (
t
RPRE
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
32) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.PER
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.PER.MIN
= – 72 ps
and
t
JIT.PER.MAX
= + 93 ps, then
t
RPRE.MIN(DERATED)
=
t
RPRE.MIN
+
t
JIT.PER.MIN
= 0.9 x
t
CK.AVG
– 72 ps = + 2178 ps and
t
RPRE.MAX(DERATED)
=
t
RPRE.MAX
+
t
JIT.PER.MAX
= 1.1 x
t
CK.AVG
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
t
JIT.DUTY
of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
t
JIT.DUTY.MIN
= – 72 ps
and
t
JIT.DUTY.MAX
= + 93 ps, then
t
RPST.MIN(DERATED)
=
t
RPST.MIN
+
t
JIT.DUTY.MIN
= 0.4 x
t
CK.AVG
– 72 ps = + 928 ps and
t
RPST.MAX(DERATED)
=
t
RPST.MAX
+
t
JIT.DUTY.MAX
= 0.6 x
t
CK.AVG
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support
t
nPARAM
= RU{
t
PARAM
/
t
CK.AVG
}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
t
nRP
= RU{
t
RP
/
t
CK.AVG
}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
RP
= 15 ns, the device will support
t
nRP
= RU{
t
RP
/
t
CK.AVG
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35)
t
WTR
is at lease two clocks (2 x
t
CK
) independent of operation frequency.
36) This timing parameter is relaxed than Industry Standard
FIGURE 3
Method for Calculating Transitions and Endpoint