Справочник Пользователя для PC Concepts SHG2 DP
Introduction
Intel® SHG2 DP Server Board Technical Product Specification
Intel Order Number C11343-001
Revision 1.0
4
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Super I/O* controller chip providing all PC-compatible I/O (floppy, parallel, serial,
keyboard, mouse).
keyboard, mouse).
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Sahalee Baseboard Management Controller (BMC) providing monitoring, alerting,
and logging of critical system information obtained from embedded sensors on
baseboard.
and logging of critical system information obtained from embedded sensors on
baseboard.
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Four Universal Serial Bus (USB) ports.
•
Two 68 pin Ultra SCSI connectors, supporting two SCSI U-160 channels
•
Two 40 pin fast ATA (IDE) connectors, supporting two ATA 33/66/100 channels
1.2 Document Structure and Outline
The information contained in this document is organized into 11 chapters. The content of each
chapter is summarized below:
chapter is summarized below:
Chapter 1:
Introduction
Architectural overview of the Intel SHG2 Server Board showing functional blocks
and identifying major features.
Architectural overview of the Intel SHG2 Server Board showing functional blocks
and identifying major features.
Chapter 2:
Processor and Chipset
Detailed description of the chipset and the supported processors.
Detailed description of the chipset and the supported processors.
Chapter 3:
Baseboard PCI I/O Subsystem
Detailed descriptions of the PCI I/O subsystem. Three PCI buses are detailed,
with specifics on embedded devices and provided slots. Interrupt routing
information is also provided.
Detailed descriptions of the PCI I/O subsystem. Three PCI buses are detailed,
with specifics on embedded devices and provided slots. Interrupt routing
information is also provided.
Chapter 4:
Clock Generation and Distribution
Identification of the clock signals generated and used on the SHG2 server board,
and detailed drawings of their implementation.
Identification of the clock signals generated and used on the SHG2 server board,
and detailed drawings of their implementation.
Chapter 5:
Server Management
Detailed description of the server management hardware integrated on the
SHG2 baseboard. I
Detailed description of the server management hardware integrated on the
SHG2 baseboard. I
2
C* addresses and block diagrams are provided.
Chapter 6:
Error Handling and Reporting
Defines how errors are handled by the system BIOS and SHG2 server board.
Chapter 7:
Jumpers
Identification and description of all jumpers used on the SHG2 server board.
Identification and description of all jumpers used on the SHG2 server board.
Chapter 8:
Connections
Identification of all connectors on the SHG2 server board, by ‘CN’ number and
manufacturer's part number. Interfacing specifics are identified where applicable.
Identification of all connectors on the SHG2 server board, by ‘CN’ number and
manufacturer's part number. Interfacing specifics are identified where applicable.
Chapter 9:
General Specifications
Description of operational parameters and considerations, and other hardware
specifications.
Description of operational parameters and considerations, and other hardware
specifications.
Chapter 10: Mechanical Specifications
Mechanical drawings of the Intel SHG2 Server Board.