Справочник Пользователя для PC Concepts SHG2 DP

Скачать
Страница из 97
Intel® SHG2 DP Server Board Technical Product Specification 
Processor and Chipset 
Revision 1.0 
Intel Order Number C11343-001 
 
 
 
 
11
2.3.3 CIOB-X2 
The Champion I/O Bridge (CIOB-X2) provides an integrated I/O bridge that provides a high-
performance data flow path between the IMB and the 64-bit I/O subsystem.
 
This subsystem 
supports 2 peer 64-bit PCI (-X) segments. 
 
Having two PCI (-X) interfaces, the CIOB-X2 is able 
to provide large and efficient I/O configurations.
  
The CIOB-X2 functions as the bridge between 
IMB and the two 64-bit PCI (-X) I/O segments or peers.
 
 
• 
The IMB interface is capable of supporting 1.6 GB/s of data bandwidth in both the 
upstream and downstream direction simultaneously. 
• 
The internal PCI (-X) arbiter implements the least-recently used algorithm to grant 
access to requesting masters. 
• 
The CIOB-X2 is a 352-pin ball-grid array (BGA) device. 
2.3.3.1 
64/100MHz I/O Subsystem  
The 64/100MHz subsystem supports the following embedded devices and connectors: 
• 
One PCI-X network interface controller—Intel 82544GC Gigabit Ethernet Controller with 
a dedicated RJ-45 connector. 
• 
Two 184-pin, 3.3 V keyed, 64-bit PCI expansion slot connectors, numbered PCIX-1 and 
PCIX-2, supporting 100-MHz 3.3V-compliant PCI-X adapters, and both 66-MHz and 33-
MHz 3.3V-compliant PCI adapters. 
2.3.3.2 
64/133 MHz I/O Subsystem  
The 64/133 MHz subsystem supports the following embedded device and connector: 
• 
Dual Channel Ultra 160 SCSI Controller—Adaptec 7899 SCSI Controller.  Note: When 
the 7899 is enabled, the PCI expansion slot connector would only be capable of running 
at 66 MHz PCI mode. 
• 
One 184-pin, 3.3 V keyed, 64-bit PCI expansion slot connector, numbered PCIX-6 
(64/133), supporting 133-MHz 3.3V PCI-X-compliant PCI-X adapters, and MROMB 
SCSI adapters. 
 
2.4  CSB5 South Bridge 
CSB5 is a multi-function PCI device, housed in a 256-pin BGA device, providing a PCI-to-LPC 
bridge, PCI IDE interface, PCI USB controller, and power management controller. Each 
function within the CSB5 has its own set of configuration registers. Once configured, each 
appears to the system as a distinct hardware controller sharing the same PCI bus interface. 
In the SHG2 server board implementation, the CSB5’s primary role is to provide the gateway to 
all PC-compatible I/O devices and features. The SHG2 uses the following CSB5 features: 
• 
PCI bus interface 
• 
LPC bus interface 
• 
IDE interface, with dual channel Ultra DMA 100 capability