Справочник Пользователя для PC Concepts SHG2 DP

After the system is turned on, the power supply will assert the PWRGD+00 signal after all 
voltage levels in the system have reached valid levels. The BMC receives PWRGD+00 and 
after approximately 500 ms, asserts RST_P6_PWRGOOD, which indicates to the processors 
and CSB5 that the power is stable. Upon RST_P6_PWRGOOD assertion, the CSB5 will toggle 
PCI reset. 

A hard reset can be initiated by resetting the system through the front panel switch. During the 
reset, the Sahalee BMC de-asserts RST_P6_PWR_GOOD. After 500 ms, it is reasserted, and 
the power-up reset sequence is completed. 

The Sahalee BMC is not reset by a hard reset. It may be reset at power-up. 

A soft reset causes the processors to begin execution in a known state without flushing caches 
or internal buffers. Soft resets can either be generated by SIO(KBD_PINITN), 
CSB5(RSB_PINITN), or by the CMIC-LE(CMIC_PINITN). 

32b PCI Slots

PSON

Power  button

R eset  button

S leep button

BASEBO ARD

M ANAG EM ENT

CO NTROLLER

(BM C)

debounce

logic

S

leep

Po
w

e

r

Re

s

e

t

PW RGD

Processor

Processor

isolation

reset

gateing

BM C video gate

(EMP,

IPMB Isolation

logic, etc)

VRD

Pgood

logic

PLL rst

logic

Sec PCI  Slots

Pri PCI Slots

Reset out

GPIO