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Table 1-60. Effect of BYTEMODE Bits on EMIF Accesses
BYTEMODE Setting
CPU Access to EMIF Register
CPU Access To External Memory
BYTEMODE = 00b (16-bit
Entire register contents are accessed
ASIZE = 01b (16-bit data bus): EMIF generates a
word access)
single 16-bit access to external memory for every
CPU word access.
CPU word access.
ASIZE = 00b (8-bit data bus): EMIF generates two
8-bit accesses to external memory for every CPU
word access.
8-bit accesses to external memory for every CPU
word access.
BYTEMODE = 01b (8-bit
Only the upper byte of the register is
ASIZE = 01b (16-bit data bus): EMIF generates a
access with high byte selected) accessed.
16-bit access to external memory for every CPU word
access; only the high byte of the EMIF data bus is
used.
access; only the high byte of the EMIF data bus is
used.
ASIZE = 00b (8-bit data bus): EMIF generates a
single 8-bit access to external memory for every CPU
word access.
single 8-bit access to external memory for every CPU
word access.
BYTEMODE = 10b (8-bit
Only the lower byte of the register is
ASIZE = 01b (16-bit data bus): EMIF generates a
access with low byte selected)
accessed.
16-bit access to external memory for every CPU word
access; only the low byte of the EMIF data bus is
used.
access; only the low byte of the EMIF data bus is
used.
ASIZE = 00b (8-bit data bus): EMIF generates a
single 8-bit access to external memory for every CPU
word access.
single 8-bit access to external memory for every CPU
word access.
The USB system control register (USBSCR) is described in
Table 1-61. Effect of USBSCR BYTEMODE Bits on USB Access
BYTEMODE Setting
CPU Access to USB Register
BYTEMODE = 00b (16-bit word access)
Entire register contents are accessed
BYTEMODE = 01b (8-bit access with high byte selected)
Only the upper byte of the register is accessed
BYTEMODE = 10b (8-bit access with low byte selected)
Only the lower byte of the register is accessed
1.7.6.1
EMIF System Control Register (ESCR) [1C33h]
The EMIF system control register (ESCR) is shown in
and described in
Figure 1-48. EMIF System Control Register (ESCR) [1C33h]
15
2
1
0
Reserved
BYTEMODE
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-62. EMIF System Control Register (ESCR) Field Descriptions
Bit
Field
Value
Description
15-2
Reserved
0
Reserved.
1-0
BYTEMODE
EMIF byte mode select bits. These bits control CPU data and program accesses to external
memory as well as CPU accesses the EMIF registers.
memory as well as CPU accesses the EMIF registers.
0
Word accesses by the CPU are allowed.
1h
Byte accesses by the CPU are allowed (high byte is selected).
2h
Byte accesses by the CPU are allowed (low byte is selected).
3h
Reserved.
76
System Control
SPRUFX5A – October 2010 – Revised November 2010
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