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Turbo PMAC/PMAC2 Software Reference
Turbo PMAC Global I-Variables
102
Bit 0: Flag Register Type Bit: If bit 0 is set to zero, the Turbo PMAC expects the flag registers to be in
the format of a PMAC-style Servo IC. Bit 0 should be set to 0 for any flags on-board a Turbo PMAC, an
Acc-24P, or an ACC24V.
the format of a PMAC-style Servo IC. Bit 0 should be set to 0 for any flags on-board a Turbo PMAC, an
Acc-24P, or an ACC24V.
If bit 0 is set to one, the Turbo PMAC expects the flag registers to be in the format of a PMAC2-style
Servo IC. Bit 0 should be set to 1 for any flag register on-board a Turbo PMAC2, an Acc-24P2, an Acc-
24V2, an Acc-24E2, or coming from a MACRO Station.
Servo IC. Bit 0 should be set to 1 for any flag register on-board a Turbo PMAC2, an Acc-24P2, an Acc-
24V2, an Acc-24E2, or coming from a MACRO Station.
If multiple flag registers are specified by non-zero settings of Ixx42 and/or Ixx43, all registers must be of
the same format.
the same format.
Bit 8: Kill on Hardware Limit Bit: If bit 8 is set to 0, the Turbo PMAC will always “abort” the motor
(controlled deceleration to closed-loop, zero-velocity, enabled state) on hitting a hardware overtravel limit
switch. If bit 8 is set to 1, the Turbo PMAC will instead “kill” the motor (immediate open-loop, zero-
output, disabled state) on hitting a hardware limit if (a) the software overtravel limit capability in that
direction is enabled (Ixx13 or Ixx14 != 0), and (b) the software overtravel limit in that direction has not
already been exceeded. Other motors are killed or aborted as determined by bits 21 and 22 of Ixx24, just
as for an amplifier fault or fatal following-error trip. If either of these conditions is not true with bit 8 set
to 1, the motor will still be aborted on hitting a hardware limit function.
(controlled deceleration to closed-loop, zero-velocity, enabled state) on hitting a hardware overtravel limit
switch. If bit 8 is set to 1, the Turbo PMAC will instead “kill” the motor (immediate open-loop, zero-
output, disabled state) on hitting a hardware limit if (a) the software overtravel limit capability in that
direction is enabled (Ixx13 or Ixx14 != 0), and (b) the software overtravel limit in that direction has not
already been exceeded. Other motors are killed or aborted as determined by bits 21 and 22 of Ixx24, just
as for an amplifier fault or fatal following-error trip. If either of these conditions is not true with bit 8 set
to 1, the motor will still be aborted on hitting a hardware limit function.
The “kill on hardware limit” function permits the software limits (set inside the hardware limits) to be
used to catch controlled moves past the limits in a manner that is easily recoverable, and the hardware
limits to catch uncontrolled moves past the limits due to feedback problems.
used to catch controlled moves past the limits in a manner that is easily recoverable, and the hardware
limits to catch uncontrolled moves past the limits due to feedback problems.
Bit 10: Third-Harmonic Injection Control Bit: If bit 10 is set to zero when the motor is controlled in
direct-PWM mode, a third-harmonic component is added to the commutation output waveforms. For
three-phase motors, this increases the operating range of the motors. If bit is set to one when the motor is
controlled in direct-PWM mode, no third-harmonic component is added. This is appropriate for the
control of two-phase motors, such as most stepper motors, for which the addition of a third-harmonic
component would add significant torque ripple without increasing operating range.
direct-PWM mode, a third-harmonic component is added to the commutation output waveforms. For
three-phase motors, this increases the operating range of the motors. If bit is set to one when the motor is
controlled in direct-PWM mode, no third-harmonic component is added. This is appropriate for the
control of two-phase motors, such as most stepper motors, for which the addition of a third-harmonic
component would add significant torque ripple without increasing operating range.
Bit 11: Capture with High-Resolution Feedback Bit: If bit 11 is set to zero when hardware position
capture is used in a triggered move such as a homing-search move, the captured data (whether whole-
count only or including sub-count data) is processed to match servo feedback of normal resolution (five
bits of fractional count data per hardware whole count). This setting is appropriate for digital quadrature
feedback or for low-resolution interpolation of a sinusoidal encoder.
capture is used in a triggered move such as a homing-search move, the captured data (whether whole-
count only or including sub-count data) is processed to match servo feedback of normal resolution (five
bits of fractional count data per hardware whole count). This setting is appropriate for digital quadrature
feedback or for low-resolution interpolation of a sinusoidal encoder.
If bit 11 (value $800, or 2,048) is set to one when hardware position capture is used in a triggered move,
the captured data (whether whole-count only or including sub-count data) is processed to match servo
feedback of high resolution (10 bits of fractional count data per hardware whole count). This setting is
appropriate for high-resolution interpolation of a sinusoidal encoder through an Acc-51x interpolator.
the captured data (whether whole-count only or including sub-count data) is processed to match servo
feedback of high resolution (10 bits of fractional count data per hardware whole count). This setting is
appropriate for high-resolution interpolation of a sinusoidal encoder through an Acc-51x interpolator.
Bit 12: Sub-Count Capture Enable Bit: If bit 12 is set to zero when hardware position capture is used
in a triggered move such as a homing-search move, only the whole-count captured position register is
used to establish the trigger position. This setting must be used with PMAC-style Servo ICs, and with
PMAC2-style Servo ICs older than Revision D (Revision D ICs started shipping in early 2002).
in a triggered move such as a homing-search move, only the whole-count captured position register is
used to establish the trigger position. This setting must be used with PMAC-style Servo ICs, and with
PMAC2-style Servo ICs older than Revision D (Revision D ICs started shipping in early 2002).
If bit 12 (value $1000, or 4,096) is set to one when hardware position capture is used in a triggered move,
both the whole-count captured position register and the estimated sub-count position register are used to
establish the trigger position. A PMAC2-style Servo IC of Revision “D” or newer must be used for this
mode, and I7mn9 for the channel used must be set to 1 to enable the hardware sub-count estimation. This
setting is typically used for registration or probing triggered moves with interpolated sinusoidal encoder
feedback. (Even with interpolated sinusoidal encoder feedback, homing search moves will probably be
done without sub-count captured data, to force a home position referenced to one of the four zero-
crossing positions of the sine/cosine signals.)
both the whole-count captured position register and the estimated sub-count position register are used to
establish the trigger position. A PMAC2-style Servo IC of Revision “D” or newer must be used for this
mode, and I7mn9 for the channel used must be set to 1 to enable the hardware sub-count estimation. This
setting is typically used for registration or probing triggered moves with interpolated sinusoidal encoder
feedback. (Even with interpolated sinusoidal encoder feedback, homing search moves will probably be
done without sub-count captured data, to force a home position referenced to one of the four zero-
crossing positions of the sine/cosine signals.)
Bit 13 Error Saturation Control Bit: If bit 13 is set to zero, when the motor’s following error exceeds
the Ixx67 position-error limit, the error is simply truncated by the limit parameter.
the Ixx67 position-error limit, the error is simply truncated by the limit parameter.