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Turbo PMAC User Manual
238
Turbo PMAC Computational Features
Priority Level Optimization
Usually, Turbo PMAC will have enough speed and calculation power to perform all of the tasks asked of
it. Some applications will put a large demand on a certain priority level, and to make Turbo PMAC run
more efficiently some priority level optimization should be done.
it. Some applications will put a large demand on a certain priority level, and to make Turbo PMAC run
more efficiently some priority level optimization should be done.
When Turbo PMAC begins to run out of time, problems such as sluggish communications, slow
PLC/PLCC scan rates, run-time errors, and even tripping the watchdog timer, can occur. The specific
solutions to the above symptoms are discussed in the sections of this manual dedicated to those subjects.
The general solution to such problems is two-fold.
PLC/PLCC scan rates, run-time errors, and even tripping the watchdog timer, can occur. The specific
solutions to the above symptoms are discussed in the sections of this manual dedicated to those subjects.
The general solution to such problems is two-fold.
First, high priority jobs could be slowed down or moved to a lower priority position. Jobs such as the
Encoder Conversion Table, PLC/PLCC0, and the Real Time Interrupt (RTI) should be evaluated. Check
to see if everything in these jobs is necessary or if some of it could be moved to a lower priority or slowed
down. For example; A 5-axis application might not need Encoder Conversion Table entries 6 to 9.
Perhaps PLC0 could be done as PLCC1, or the RTI could be done every 4th or 5th servo cycle.
Encoder Conversion Table, PLC/PLCC0, and the Real Time Interrupt (RTI) should be evaluated. Check
to see if everything in these jobs is necessary or if some of it could be moved to a lower priority or slowed
down. For example; A 5-axis application might not need Encoder Conversion Table entries 6 to 9.
Perhaps PLC0 could be done as PLCC1, or the RTI could be done every 4th or 5th servo cycle.
Second, the jobs could be adjusted to a priority level that gives them less emphasis. Large PLC programs
can be split into a few shorter PLC programs. This increases the frequency of housekeeping and
communications by giving more breaks in PLC scans. Motion program WHILE(condition)WAIT
statements could be done as follows;
can be split into a few shorter PLC programs. This increases the frequency of housekeeping and
communications by giving more breaks in PLC scans. Motion program WHILE(condition)WAIT
statements could be done as follows;
WHILE(condition)
DWELL20
ENDWHILE
This will give more time to other tasks of equal or lower priority such as PLC programs and
communications.
communications.
Evaluating the Turbo PMAC’s Computational Load
Turbo PMAC controllers offer facilities that permit you to calculate the computational loads you are
putting on the processor. There are several key timer registers to use in calculating these loads. These
registers are scaled so that one increment of the timer is two clock cycles of the DSP. So if the DSP were
running at a clock frequency of exactly 80 MHz – a clock period of 12.5 nsec – one increment of the
timer would be 25 nsec.
putting on the processor. There are several key timer registers to use in calculating these loads. These
registers are scaled so that one increment of the timer is two clock cycles of the DSP. So if the DSP were
running at a clock frequency of exactly 80 MHz – a clock period of 12.5 nsec – one increment of the
timer would be 25 nsec.
The DSP’s clock frequency is multiplied up from the crystal clock frequency of 19.66 MHz, using the
saved value of I52, according to the formula:
saved value of I52, according to the formula:
(
)
1
52
I
*
2
MHz
66
.
19
cy
DSPfrequen
+
=
In terms of period, the timer increment – 2 DSP cycles – can be calculated as:
(
)
1
52
I
4
.
203
sec
n
ment
TimerIncre
+
=
Phase Interrupt Tasks
There are two key timer registers for evaluating the computational load of the phase-interrupt tasks such
as commutation, current-loop closure, and ADC de-multiplexing. The first is a hardware timer in the
DSP, at address X:$FFFF8C. This register holds the number of timer increments between the last two
phase interrupts, establishing the period of the phase interrupt. This can be used to verify the phase
period you think you have, and with other registers, computational duty cycles.
as commutation, current-loop closure, and ADC de-multiplexing. The first is a hardware timer in the
DSP, at address X:$FFFF8C. This register holds the number of timer increments between the last two
phase interrupts, establishing the period of the phase interrupt. This can be used to verify the phase
period you think you have, and with other registers, computational duty cycles.
The second register, located at X:$000037, holds the number of timer increments from the beginning to
the end of the phase-interrupt tasks for the last interrupt. When divided by the time between phase
interrupts, this will give the duty cycle of the phase-interrupt tasks.
the end of the phase-interrupt tasks for the last interrupt. When divided by the time between phase
interrupts, this will give the duty cycle of the phase-interrupt tasks.