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Turbo PMAC User Manual
390
Writing a Host Communications Program
Interrupt Controller Structure
The PIC appears as four 8-bit registers in the I/O space of the PC. The actual address of these registers
depends on the setting of the base address (Base) of the Turbo PMAC in the I/O space of the PC. For
ISA-bus Turbo PMACs, this base address is set by jumpers (Turbo PMAC) or by DIP-switches (Turbo
PMAC2) on the controller. For PCI-bus Turbo PMACs, this base address is set by the PC’s operating
system during the PC’s initialization.
The PIC appears as four 8-bit registers in the I/O space of the PC. The actual address of these registers
depends on the setting of the base address (Base) of the Turbo PMAC in the I/O space of the PC. For
ISA-bus Turbo PMACs, this base address is set by jumpers (Turbo PMAC) or by DIP-switches (Turbo
PMAC2) on the controller. For PCI-bus Turbo PMACs, this base address is set by the PC’s operating
system during the PC’s initialization.
These four registers in the PIC are:
•
Base+8:
Interrupt Status Register
•
Base+9:
Interrupt Signal Status Register
•
Base+10: Interrupt Mask Control Register
•
Base+11: Interrupt Edge/Level Control Register
For example, with the ISA-bus base address at the factory default of 528 (210 hex), these four registers
are at 536-539 (218-21B hex).
are at 536-539 (218-21B hex).
The eight bits (0 – 7) in each register represent the status or control of the eight interrupt source signals
wired into the PIC lines IR0 – IR7.
wired into the PIC lines IR0 – IR7.
Interrupt Controller Registers
Interrupt Status Register (Base+8): This register, when read, shows the status of the eight interrupts. It
will be read by any interrupt service routine to find out which signal created the interrupt to the PC. A 1
in a bit indicates an interrupt for the matching signal; a 0 indicates no interrupt. An interrupt signal must
be unmasked before it can show an interrupt in this register. The act of writing to this register will clear
any edge-triggered interrupts, no matter what value is written.
Interrupt Status Register (Base+8): This register, when read, shows the status of the eight interrupts. It
will be read by any interrupt service routine to find out which signal created the interrupt to the PC. A 1
in a bit indicates an interrupt for the matching signal; a 0 indicates no interrupt. An interrupt signal must
be unmasked before it can show an interrupt in this register. The act of writing to this register will clear
any edge-triggered interrupts, no matter what value is written.
Interrupt Signal Status Register (Base+9): This register, when read, shows the status of the eight signal
inputs to the PIC. It is not useful in interrupt service routines, but provides a fast and easy method for
polling the status of these signals without any overhead to the Turbo PMAC.
inputs to the PIC. It is not useful in interrupt service routines, but provides a fast and easy method for
polling the status of these signals without any overhead to the Turbo PMAC.
Interrupt Mask Control Register (Base+10): This register permits the PC to mask out interrupt signals
that the user does not want to interrupt the PC. In the ISA-bus Turbo PMAC-PC, writing a 0 to a bit in
this register enables the corresponding signal to interrupt the PC; writing a 1 to a bit in this register
disables (masks out) that signal. In all other Turbo PMACs, writing a 1 to a bit in this register enables the
corresponding signal to interrupt the PC; writing a 0 to a bit in this register disables (masks out) that
signal. This register can be read at any time to find which signals are masked without affecting the
masking.
that the user does not want to interrupt the PC. In the ISA-bus Turbo PMAC-PC, writing a 0 to a bit in
this register enables the corresponding signal to interrupt the PC; writing a 1 to a bit in this register
disables (masks out) that signal. In all other Turbo PMACs, writing a 1 to a bit in this register enables the
corresponding signal to interrupt the PC; writing a 0 to a bit in this register disables (masks out) that
signal. This register can be read at any time to find which signals are masked without affecting the
masking.
Interrupt Edge/Level Control Register (Base+11): This register permits the PC to control whether an
interrupt signal interrupts the PC on an edge-triggered basis or by level. Writing a 1 to a bit in this
register sets the corresponding signal for a level-triggered interrupt; writing a 0 to a bit in this register sets
that signal for an edge-triggered interrupt. Edge-triggered interrupts are the default, and are typically
more useful.
interrupt signal interrupts the PC on an edge-triggered basis or by level. Writing a 1 to a bit in this
register sets the corresponding signal for a level-triggered interrupt; writing a 0 to a bit in this register sets
that signal for an edge-triggered interrupt. Edge-triggered interrupts are the default, and are typically
more useful.
If an interrupt is edge-triggered, in order for that signal to generate another interrupt to the PC (after the
PC clears the interrupts by writing to Base+8), the signal must go low, then high again. If an interrupt is
level-triggered, if the signal is still high after the PC clears the interrupts, it will immediately interrupt the
PC again.
PC clears the interrupts by writing to Base+8), the signal must go low, then high again. If an interrupt is
level-triggered, if the signal is still high after the PC clears the interrupts, it will immediately interrupt the
PC again.
Discrete Interrupt Controller
The Turbo PMAC-PC for the ISA bus uses a discrete 8259 interrupt controller, identical to the circuitry
used in the interrupt controllers in the PC itself. The following section explains the steps for using this IC
in the Turbo PMAC; more detailed information can be found in documentation for any 8259 IC.
used in the interrupt controllers in the PC itself. The following section explains the steps for using this IC
in the Turbo PMAC; more detailed information can be found in documentation for any 8259 IC.