Справочник Пользователя для Intel Pentium 4 530 3.0GHz HT LGA FSB800 1MB BX80547PG3000E/BOXD915PBLL
Модели
BX80547PG3000E/BOXD915PBLL
Intel Desktop Board D915PBL Technical Product Specification
56
Table 14.
PCI Interrupt Routing Map
ICH6-R PIRQ Signal Name
PCI Interrupt Source
PIRQA
PIRQB
PIRQC
PIRQD
PIRQE
PIRQF
PIRQG
PIRQH
IEEE-1394a controller
INTA
PCI bus connector 1
INTD
INTA
INTB
INTC
PCI bus connector 2
INTC
INTB
INTA
INTD
PCI bus connector 3
INTD
INTC
INTA
INTB
PCI bus connector 4
INTB
INTA
INTC
INTD
✏
NOTE
In PIC mode, the ICH6-R can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5,
6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 13 for the
allocation of PIRQ lines to IRQ signals in APIC mode.
6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a
unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or
more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 13 for the
allocation of PIRQ lines to IRQ signals in APIC mode.
PCI interrupt assignments to the USB ports, Serial ATA ports, and PCI Express ports are dynamic.