Техническая Спецификация для Intel Celeron BX80526F733128
Модели
BX80526F733128
34
Datasheet
Intel
®
Celeron
®
Processor up to 1.10 GHz
2.12
System Bus AC Specifications
The Celeron processor system bus timings specified in this section are defined at the Intel Celeron
processor edge fingers and the processor core pins. Timings specified at the processor edge fingers
only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P.
Package and PGA packages. Unless otherwise specified, timings are tested at the processor core
during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See
processor edge fingers and the processor core pins. Timings specified at the processor edge fingers
only apply to the S.E.P. Package and timings given at the processor core pins apply to all S.E.P.
Package and PGA packages. Unless otherwise specified, timings are tested at the processor core
during manufacturing. Timings at the processor edge fingers are specified by design
characterization. See
for the Intel Celeron processor signal definitions. Note that at
66 MHz system bus operation, the Intel Celeron processor timings at the processor edge
fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium
fingers are identical to the Pentium II processor timings at the edge fingers. See the Pentium
®
II Processor at 233, 266, 300, and 333 MHz (Order Number 243335) for more detail.
through
list the AC specifications associated with the Intel Celeron processor
through
contain the system bus clock specifications,
contain the AGTL+
and
are the CMOS signal group specifications,
contains
timings for the Reset conditions,
and
cover APIC bus timing, and
cover TAP timing. For each pair of tables, the first table contains timing specifications for
measurement or simulation at the processor edge fingers. The second table contains specifications
for simulation at the processor core pads.
for simulation at the processor core pads.
All Intel Celeron processor system bus AC specifications for the AGTL+ signal group are relative
to the rising edge of the BCLK input. All AGTL+ timings are referenced to V
to the rising edge of the BCLK input. All AGTL+ timings are referenced to V
REF
for both ‘0’ and
‘1’ logic levels unless otherwise specified.
The timings specified in this section should be used in conjunction with the I/O buffer models
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel Celeron
provided by Intel. These I/O buffer models, which include package information, are available in
Quad format as the Intel Celeron
®
Processor I/O Buffer Models, Quad XTK Format (Electronic
Form). AGTL+ layout guidelines are also available in AP-585, Pentium
®
II Processor AGTL+
Guidelines (Order Number 243330).
Care should be taken to read all notes associated with a particular timing parameter.