Справочник Пользователя для Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430

Intel® Xeon® Processor 3400 Series Datasheet, Volume 2

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7

RO

0

Fast Back-to-Back Enable
Not applicable to PCI Express. This bit is hardwired to 0. 

6

RW

0

Secondary Bus Reset
0 = No reset happens on the PCI Express port.

1 = Setting this bit triggers a hot reset on the link for the corresponding PCI 

Express port and the PCI Express hierarchy domain subordinate to the 

port. This sends the LTSSM into the Training (or Link) Control Reset state, 

which necessarily implies a reset to the downstream device and all 

subordinate devices. The transaction layer corresponding to port will be 

emptied by Integrated I/O when this bit is set. This means that in the 

outbound direction, all posted transactions are dropped and non-posted 

transactions are sent a UR response. In the inbound direction, 

completions for inbound NP requests are dropped when they arrive. 

Inbound posted writes are required to be flushed as well either by 

dropping the packets are by retiring them normally.

Note also that a secondary bus reset will not reset the virtual PCI-to-PCI 

bridge configuration registers of the targeted PCI Express port. 

5

RO

0

Master Abort Mode
Not applicable to PCI Express. This bit is hardwired to 0. 

4

RW

0

VGA 16-bit Decode
This bit enables the virtual PCI-to-PCI bridge to provide 16-bit decoding of 

VGA I/O address precluding the decoding of alias addresses every 1 KB.
0 = Execute 10-bit address decodes on VGA I/O accesses.

1 = Execute 16-bit address decodes on VGA I/O accesses.
This bit only has meaning if bit 3 of this register is also set to 1, enabling VGA 

I/O decoding and forwarding by the bridge.
Refer to the PCI-to-PCI Bridge Specification for further details of this bit 

behavior.

3

RW

0

VGA Enable
This bit controls the routing of processor initiated transactions targeting VGA 

compatible I/O and memory address ranges. This bit must only be set for one 

PCI Express port.

2

RW

0

ISA Enable
Modifies the response by the Integrated I/O to an I/O access issued by the 

processor that target ISA I/O addresses. This applies only to I/O addresses 

that are enabled by the IOBASE and IOLIM registers.
0 = All addresses defined by the IOBASE and IOLIM for processor I/O 

transactions will be mapped to PCI Express.

1 = The Integrated I/O will not forward to PCI Express any I/O transactions 

addressing the last 768 bytes in each 1-KB block even if the addresses 

are within the range defined by the IOBASE and IOLIM registers. 

1

RW

0

SERR Enable
This bit controls forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL 

messages from the PCI Express* port to the primary side.
0 = Disables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL.

1 = Enables forwarding of ERR_COR, ERR_NONFATAL and ERR_FATAL 

messages. 

0

RW

0

Parity Error Response Enable
The Integrated I/O ignores this bit. This bit though affects the setting of Bit 8 

in the SECSTS register.