Справочник Пользователя для Intel Xeon® Processor X3430 (8M Cache, 2.40 GHz) BX80605X3430
Модели
BX80605X3430
Processor Integrated I/O (IIO) Configuration Registers
52
Intel® Xeon® Processor 3400 Series Datasheet, Volume 2
3.3.4.8
MSICTRL—MSI Control Register
Register:
MSICTRL
Device:
0 (DMI), 3-6 (PCIe)
Function: 0
Offset:
62h
Bit
Attr
Default
Description
15:9
RV
00h
Reserved
8
RO
1
Reserved
7
RO
0
64-bit Address Capable
This field is hardwired to 0h since the message addresses are only 32-bit
This field is hardwired to 0h since the message addresses are only 32-bit
addresses (for example, FEEx_xxxxh).
6:4
RW
000
Multiple Message Enable
Applicable only to PCI Express* ports. Software writes to this field to indicate
Applicable only to PCI Express* ports. Software writes to this field to indicate
the number of allocated messages which is aligned to a power of two. When
MSI is enabled, the software will allocate at least one message to the device. A
value of 000 indicates 1 message. Any value greater than or equal to 001
indicates a message of 2.
3:1
RO
001
Multiple Message Capable
Integrated I/O Express ports support two messages for all their internal
Integrated I/O Express ports support two messages for all their internal
events.
0
RW
0
MSI Enable
The software sets this bit to select platform-specific interrupts or transmit MSI
The software sets this bit to select platform-specific interrupts or transmit MSI
messages.
0 = Disables MSI from being generated.
0 = Disables MSI from being generated.
1 = MSI will be generated when appropriate conditions occur.