Справочник Пользователя для Intel Xeon X3470 BX80605X3470
Модели
BX80605X3470
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
13
Introduction
1.2.2
PCI Express*
• The processor PCI Express* port(s) are fully-compliant with the PCI Express Base
Specification, Revision 2.0.
• Intel
®
Xeon
®
processor 3400 series with Intel 3420 Chipset supports:
— One 16-lane PCI Express port intended for graphics or I/O.
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
• Intel
®
Xeon
®
processor 3400 series with Intel 3400 Chipset supports:
— Two 8-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
— Four 4-lane PCI Express ports intended for I/O.
• PCI Express port 0 is mapped to PCI Device 3.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
• PCI Express port 1 is mapped to PCI Device 5.
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x1 widths for a single PCI Express mode.
• 2.5 GT/s and 5.0 GT/s PCI Express frequencies are supported.
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
• Either port can be configured independently as 2.5 GT/s or 5.0 GT/s.
• Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of
500 MB/s given the 8b/10b encoding used to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 8 GB/s in each direction
simultaneously, for an aggregate of 16 GB/s for x16.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express Enhanced Access Mechanism. Accessing the device configuration space
in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X* Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— PCI Express Port 0 -> PCI Express Port 1
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
— PCI Express Port 1 -> PCI Express Port 0
— DMI -> PCI Express Port 0
— DMI -> PCI Express Port 1
— PCI Express Port 1 -> DMI
— PCI Express Port 0 -> DMI
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.