Справочник Пользователя для Intel Xeon X3470 BX80605X3470
Модели
BX80605X3470
Intel® Xeon® Processor 3400 Series Datasheet, Volume 1
49
Signal Description
Table 6-3.
Memory Channel B
Signal Name
Description
Direction
Type
SB_BS[2:0]
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O
DDR3
SB_CAS#
CAS Control Signal: Used with SB_RAS# and SB_WE#
(along with SB_CS#) to define the SDRAM Commands.
O
DDR3
SB_CK#[1:0]
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
O
DDR3
SB_CK#[3:2]
SDRAM Inverted Differential Clock: Channel B SDRAM
Differential clock signal-pair complement.
O
DDR3
SB_CK[1:0]
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
O
DDR3
SB_CK[3:2]
SDRAM Differential Clock: Channel B SDRAM Differential
clock signal pair.
The crossing of the positive edge of SB_CKx and the
The crossing of the positive edge of SB_CKx and the
negative edge of its complement SB_CKx# are used to
sample the command and control signals on the SDRAM.
O
DDR3
SB_CKE[3:0]
Clock Enable: (1 per rank) used to:
• Initialize the SDRAMs during power-up
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
• Power-down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh
during STR
O
DDR3
SB_CS#[3:0]
Chip Select: (1 per rank) Used to select particular SDRAM
components during the active state. There is one Chip
Select for each SDRAM rank.
O
DDR3
SB_CS#[7:4]
These signals are only used for processors and platforms
that have Registered DIMM support. These signals are
used to select particular SDRAM components during the
active state and SB_CS#[7:6] are used as the on die
termination for the first DIMM.
O
DDR3
SB_DM[7:0]
Data Mask: These signals are used to mask individual
bytes of data in the case of a partial write, and to
interrupt burst writes. When activated during writes, the
corresponding data groups in the SDRAM are masked.
There is one SB_DM[7:0] for every data byte lane.
Note: These signals are not used by the Intel Xeon
Note: These signals are not used by the Intel Xeon
processor 3400 series. They are connected to V
SS
on the
package.
SB_DQ[63:0]
Data Bus: Channel B data signal interface to the SDRAM
data bus.
I/O
DDR3
SB_DQS[8:0]
SB_DQS#[8:0]
Data Strobes: SB_DQS[8:0] and its complement signal
group make up a differential strobe pair. The data is
captured at the crossing point of SB_DQS[8:0] and its
SB_DQS#[8:0] during read and write transactions.
I/O
DDR3
SB_ECC_CB[7:0]
Data Lines for ECC Check Byte.
I/O
DDR3
SB_MA[15:0]
Memory Address: These signals are used to provide the
multiplexed row and column address to the SDRAM.
O
DDR3
SB_ODT[3:0]
On-Die Termination: Active Termination Control.
O
DDR3
SB_RAS#
RAS Control Signal: Used with SB_CAS# and SB_WE#
(along with SB_CS#) to define the SDRAM Commands.
O
DDR3
SB_WE#
Write Enable Control Signal: Used with SB_RAS# and
SB_CAS# (along with SB_CS#) to define the SDRAM
Commands.
O
DDR3