Справочник Пользователя для Intel Core™ i5-750 Processor (8M Cache, 2.66 GHz) BX8060515750
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BX8060515750
Datasheet, Volume 2
155
Processor Integrated I/O (IIO) Configuration Registers
3.5.2.27
FLTREC[10,7:0]—Fault Record Register
FLTREC[10] register is for the Isochronous Intel VT-d engine and [7:0] registers are for
non-isochronous Intel VT-d engine.
non-isochronous Intel VT-d engine.
3.5.2.28
INVADDRREG[0:1]—Invalidate Address Register
Register: FLTREC[10,7:0]
Addr: MMIO
BAR: VTBAR
Offset:
1100h, 170h,160h,150h,140h,130h,120h,110h,100h
Bit
Attr
Default
Description
127
RW1CS
0
Fault (F)
Hardware sets this field to indicate a fault is logged in this fault recording
Hardware sets this field to indicate a fault is logged in this fault recording
register. When this field is set, hardware may collapse additional faults from
the same requestor (SID).
Software writes the value read from this field to clear it.
Software writes the value read from this field to clear it.
126
RO
0
Reserved
125:124
RO
0
Reserved
123:104
RV
0
Reserved
103:96
ROS
0
Fault Reason
Reason for the first translation fault. See Intel
Reason for the first translation fault. See Intel
VT-d specification for details.
This field is only valid when Fault bit is set.
95:80
RV
0
Reserved
79:64
ROS
0
Source Identifier
Requester ID that faulted. Valid only when F bit is set.
Requester ID that faulted. Valid only when F bit is set.
63:12
ROS
0
GPA
4-K aligned GPA for the faulting transaction. Valid only when F field is set.
4-K aligned GPA for the faulting transaction. Valid only when F field is set.
11:0
RV
0
Reserved
Register: INVADDRREG[0:1]
Addr: MMIO
BAR: VTBAR
Offset:
200h, 1200h
Bit
Attr
Default
Description
63:12
RW
0
Address (ADDR)
To request a page-specific invalidation request to hardware, software must first
To request a page-specific invalidation request to hardware, software must first
write the corresponding guest physical address to this register, and then issue a
page-specific invalidate command through the IOTLBINV register.
11:7
RV
0
Reserved
6
RW
0
Invalidation Hint
The field provides hint to hardware to preserve or flush the respective non-leaf
The field provides hint to hardware to preserve or flush the respective non-leaf
page-table entries that may be cached in hardware.
0 = Software may have modified both leaf and non-leaf page-table entries
0 = Software may have modified both leaf and non-leaf page-table entries
corresponding to mappings specified in the ADDR and AM fields. On a page-
selective invalidation request, IIO must flush both the cached leaf and
nonleaf page-table entries corresponding to mappings specified by ADDR
and AM fields. IIO performs a domain-level invalidation on non-leaf entries
and page-selective-domain-level invalidation at the leaf level
1 = Software has not modified any non-leaf page-table entries corresponding to
mappings specified in the ADDR and AM fields. On a page-selective
invalidation request, IIO preserves the cached non-leaf page-table entries
corresponding to mappings specified by ADDR and AM fields and performs
only a page-selective invalidation at the leaf level.
5:0
RW
0
Address Mask (AM)
IIO supports values of 0-9. All other values result in undefined results.
IIO supports values of 0-9. All other values result in undefined results.