Справочник Пользователя для Renesas R5S72641
Section 9 Bus State Controller
Page 248 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
20 BAS 0 R/W
SRAM with Byte Selection Byte Access Select
Specifies the
Specifies the
WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the
WEn signal at the read/write timing and
asserts the RD/
WR signal during the write access
cycle.
1: Asserts the
WEn signal during the read/write
access cycle and asserts the RD/
WR signal at the
write timing.
19, 18
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
These bits are always read as 0. The write value
should always be 0.
17, 16
*
All 0
R/W
Reserved
Set these bits to 0 when the interfaces for normal
space or for SRAM with byte selection are used.
space or for SRAM with byte selection are used.
15 to 13
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
should always be 0.
12, 11
SW[1:0]
00
R/W
Number of Delay Cycles from Address,
CS0 Assertion
to
RD, WEn Assertion
Specify the number of delay cycles from address and
CS0 assertion to RD and WEn assertion.
00: 0.5 cycles
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles