Справочник Пользователя для Mitsubishi Electronics MELSEC Q series MELSEC L series
8-24
8.2 Counter Function Dedicated Instruction
8.2.6 ICCOVWR instruction
8.2.6 ICCOVWR instruction
ICCOVWR1, ICCOVWR2
8.2.6
ICCOVWR instruction
ICCOVWR1, ICCOVWR2
Function
This instruction stores a coincidence output No. n point of the specified CH (refer to the
following).
• ICCOVWR1(P): CH1
• ICCOVWR2(P): CH2
following).
• ICCOVWR1(P): CH1
• ICCOVWR2(P): CH2
Program Example
The following program sets the value of D100 and D101 to the coincidence output No. 2 point of
CH 1 when M0 turns ON.
CH 1 when M0 turns ON.
[Structured ladder/FBD]
[ST]
ICCOVWR1(M0, 2, D100);
ICCOVWR1(M0, 2, D100);
ICCOVWR1(P)
ICCOVWR2(P)
ICCOVWR2(P)
P: Executing condition
:
indicates any of the following
instructions.
ICCOVWR1
ICCOVWR1P
ICCOVWR2
ICCOVWR2P
Input argument
EN:
Executing condition
:Bit
n:
Coincidence output No. n point (1,2)
:ANY16
s:
Coincidence output No. n point (constant), or start number of
the device in which coincidence output No. n point is stored
the device in which coincidence output No. n point is stored
• Constant: Settings which is within the range of -2147483648
to 2147483647
• Device: Within the range of specified device
:ANY32
Output argument
ENO:
Execution result
:Bit
Setting
data
Internal device
R, ZR
J
\
U
\G
Zn
Constant
Others
Bit
Word
Bit
Word
n
LCPU
ST
ICCOVWR1
EN
ENO
n
s
ICCOVWR1
(EN, n, s);
ENO:=
Structured ladder/FBD
s