Справочник Пользователя для Mitsubishi Electronics FX

FX Series Programmable Controlers

Applied Instructions 5

5-100

5.9.5

CCD (FNC 84)

Operation:

This instruction looks at a byte (8 bit) stack of data
from head address (S)for n bytes and checks the
vertical bit pattern for parity and sums the total
data stack. These two pieces of data are then
stored at the destination (D).

Points to note:

a) The SUM of the data stack is stored at destination D while the Parity for the data stack is

stored at D

b) During the Parity check an even result is indicated by the use of a 0 (zero) while an odd

parity is indicated by a 1 (one).

c) This instruction can be used with the 8 bit/ 16 bit mode flag M8161. The following results will

occur under these circumstances. See page 10-20 for more details about M8161.

It should be noted that when M8161 is OFF ‘n’ represents the number of consecutive bytes
checked by the CCD instruction. When M8161 is ON only the lower bytes of ‘n’ consecutive
words are used.
The ‘SUM’ is quite simply a summation of the total quantity of data in the data stack. The Parity
is checked vertically through the data stack as shown by the shaded areas.

Mnemonic

Function

Operands

Program steps

CCD
FNC 84
(Check
Code)

Checks the
‘vertical’ parity of
a data stack

KnX, KnY, KnM,
KnS
T, C, D

KnY, KnM, KnS
T, C, D

K, H
D
Note:
n = 1 to 256

CCD,
CCDP:
7 steps

0(S)

FX FX

(2C)

2N(C)

(2C)

2N(C)

0(s)

PULSE-P

(2C)

2N(C)

0(s)

16 BIT OPERATION

0(s)

(2C)

2N(C)

32 BIT OPERATION

K 6

[ S ]

[ D ]

CCD D100

[ n ]

D100

M8161=OFF

Sourse (S)

Bit patterm

H
L

D101

H
L

D102

H
L

Vertical

party

SUM D0

3FC

D100 L

M8161=ON

Sourse (S)

Bit patterm

Vertical

party

SUM D0

2FD

D101 L

D102 L

D103 L

D104 L

D105 L