Справочник Пользователя для Fujitsu FR20

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CHAPTER 6  FG Input

[bit2]:DPGD

It is DPG input edge detection flag. 

[bit1]:DPCLR 

This is the clear bit of DPG input edge detection flag.

The read value of this bit is always "1".

[bit0]:DPGE

This is the initialization control bit for the programmable divider using DPG input. 

■

[bit7 to 4]: 

It is an unused bit.

[bit3 to 0]:DIV3 to 0 

Division control of the drum input and edge detection control are performed by the set value. 

0 

DPG Input None

1 DPG 

input 

0 

Clear the DPGD flag.

1 None

0 

Not initialize by DPG input

1 

Initialize by DPG input

7 6 5 4 3 2 1 0 

---- XXXX

B

Initial value

bit

DIV3

DIV2

DIV1

DIV0

R/W

R/W

R/W

Access

Address: 000054

H

Set value

Division control

Edge detection

00

H

None

Both edge detection

01

H

1-frequency division

Rising edge detection 

02

H

2-frequency division

03

H

3-frequency division

to to 

0D

H

13-frequency division

0E

H

14-frequency division

0F

H

15-frequency division